Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	1980	1			T9	15		T47	9		T48	4
auto[PWRUP]	133	1			T9	3		T47	2		T58	5
auto[ONEST_0]	72	1			T58	1		T14	1		T31	1
auto[ONEST_021]	13	1			T97	1		T15	1		T42	1
auto[ONEST_1]	65	1			T47	1		T31	1		T64	1
auto[ONEST_DONE]	1	1			T372	1		-	-		-	-
auto[LP_0]	119	1			T9	2		T47	1		T58	1
auto[LP_021]	25	1			T9	1		T58	1		T64	1
auto[LP_1]	115	1			T9	3		T58	1		T64	2
auto[LP_EVAL]	60	1			T9	2		T47	1		T58	1
auto[LP_SLP]	459	1			T9	5		T47	6		T58	8
auto[LP_PWRUP]	19	1			T47	2		T59	1		T42	2
auto[NP_0]	164	1			T9	2		T47	1		T58	2
auto[NP_021]	43	1			T59	1		T15	1		T39	1
auto[NP_1]	184	1			T9	2		T47	2		T58	3
auto[NP_EVAL]	16	1			T176	1		T42	1		T53	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

8

1

T47

1

T373

1

T374

1

min

1649

1

T9

7

T47

8

T48

4

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1661	1			T9	7		T47	8		T48	4
pow[0x1]	11	1			T39	2		T42	1		T63	1
pow[0x2]	15	1			T58	1		T375	1		T376	1
pow[0x3]	28	1			T9	1		T58	1		T31	2
pow[0x4]	54	1			T58	1		T59	2		T176	1
pow[0x5]	113	1			T9	1		T47	2		T58	2
pow[0x6]	241	1			T9	5		T47	3		T58	4
pow[0x7]	417	1			T9	2		T47	3		T58	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

175

1

T9

5

T47

2

T58

1

min

1184

1

T9

2

T47

3

T48

4

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1189	1			T9	2		T47	3		T48	4
pow[0x1]	15	1			T15	1		T295	1		T121	1
pow[0x2]	17	1			T51	1		T52	1		T53	1
pow[0x3]	18	1			T45	1		T49	1		T50	1
pow[0x4]	13	1			T45	1		T51	2		T53	2
pow[0x5]	1	1			T39	1		-	-		-	-
pow[0x7]	1	1			T377	1		-	-		-	-
pow[0x8]	8	1			T42	1		T374	1		T378	1
pow[0x9]	6	1			T60	1		T376	1		T232	1
pow[0xa]	15	1			T39	1		T238	1		T229	1
pow[0xb]	28	1			T9	2		T47	1		T58	1
pow[0xc]	58	1			T9	2		T58	1		T64	1
pow[0xd]	129	1			T9	1		T58	2		T31	2
pow[0xe]	265	1			T9	3		T47	5		T58	6
pow[0xf]	490	1			T9	4		T47	3		T58	8