Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1850	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1919	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1925	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1902	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2033	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1805	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1837	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2025	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1791	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2032	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1949	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1854	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1759	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1894	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1736	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1864	0	0
adc_en_ctl_rd_A	2147483647	1699	0	0
adc_fsm_rst_rd_A	2147483647	1588	0	0
adc_intr_ctl_rd_A	2147483647	2096	0	0
adc_lp_sample_ctl_rd_A	2147483647	1673	0	0
adc_pd_ctl_rd_A	2147483647	1683	0	0
adc_sample_ctl_rd_A	2147483647	1478	0	0
adc_wakeup_ctl_rd_A	2147483647	1739	0	0
intr_enable_rd_A	2147483647	2183	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1850	0	0
T14	225240	18	0	0
T15	0	38	0	0
T16	0	5	0	0
T17	0	23	0	0
T18	0	13	0	0
T19	0	34	0	0
T20	0	22	0	0
T21	0	22	0	0
T22	0	15	0	0
T23	0	35	0	0
T24	231678	0	0	0
T25	25099	0	0	0
T26	914799	0	0	0
T27	470748	0	0	0
T28	811128	0	0	0
T29	325767	0	0	0
T30	117089	0	0	0
T31	626292	0	0	0
T32	494258	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1919	0	0
T14	225240	25	0	0
T15	0	32	0	0
T16	0	11	0	0
T17	0	18	0	0
T18	0	19	0	0
T19	0	31	0	0
T20	0	14	0	0
T21	0	21	0	0
T22	0	17	0	0
T23	0	55	0	0
T24	231678	0	0	0
T25	25099	0	0	0
T26	914799	0	0	0
T27	470748	0	0	0
T28	811128	0	0	0
T29	325767	0	0	0
T30	117089	0	0	0
T31	626292	0	0	0
T32	494258	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1925	0	0
T14	225240	4	0	0
T15	0	34	0	0
T16	0	10	0	0
T17	0	22	0	0
T18	0	5	0	0
T19	0	29	0	0
T20	0	20	0	0
T21	0	22	0	0
T22	0	15	0	0
T23	0	48	0	0
T24	231678	0	0	0
T25	25099	0	0	0
T26	914799	0	0	0
T27	470748	0	0	0
T28	811128	0	0	0
T29	325767	0	0	0
T30	117089	0	0	0
T31	626292	0	0	0
T32	494258	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1902	0	0
T14	225240	14	0	0
T15	0	25	0	0
T16	0	4	0	0
T17	0	33	0	0
T18	0	20	0	0
T19	0	25	0	0
T20	0	22	0	0
T21	0	16	0	0
T22	0	24	0	0
T23	0	36	0	0
T24	231678	0	0	0
T25	25099	0	0	0
T26	914799	0	0	0
T27	470748	0	0	0
T28	811128	0	0	0
T29	325767	0	0	0
T30	117089	0	0	0
T31	626292	0	0	0
T32	494258	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2033	0	0
T14	225240	10	0	0
T15	0	36	0	0
T16	0	18	0	0
T17	0	44	0	0
T18	0	24	0	0
T19	0	47	0	0
T20	0	12	0	0
T21	0	15	0	0
T22	0	31	0	0
T23	0	22	0	0
T24	231678	0	0	0
T25	25099	0	0	0
T26	914799	0	0	0
T27	470748	0	0	0
T28	811128	0	0	0
T29	325767	0	0	0
T30	117089	0	0	0
T31	626292	0	0	0
T32	494258	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1805	0	0
T14	225240	7	0	0
T15	0	45	0	0
T16	0	8	0	0
T17	0	19	0	0
T18	0	14	0	0
T19	0	32	0	0
T20	0	26	0	0
T21	0	13	0	0
T22	0	11	0	0
T23	0	44	0	0
T24	231678	0	0	0
T25	25099	0	0	0
T26	914799	0	0	0
T27	470748	0	0	0
T28	811128	0	0	0
T29	325767	0	0	0
T30	117089	0	0	0
T31	626292	0	0	0
T32	494258	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1837	0	0
T14	225240	7	0	0
T15	0	48	0	0
T16	0	11	0	0
T17	0	27	0	0
T18	0	20	0	0
T19	0	28	0	0
T20	0	13	0	0
T21	0	10	0	0
T22	0	22	0	0
T23	0	40	0	0
T24	231678	0	0	0
T25	25099	0	0	0
T26	914799	0	0	0
T27	470748	0	0	0
T28	811128	0	0	0
T29	325767	0	0	0
T30	117089	0	0	0
T31	626292	0	0	0
T32	494258	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2025	0	0
T14	225240	14	0	0
T15	0	25	0	0
T16	0	27	0	0
T17	0	36	0	0
T18	0	20	0	0
T19	0	40	0	0
T20	0	12	0	0
T21	0	16	0	0
T22	0	20	0	0
T23	0	38	0	0
T24	231678	0	0	0
T25	25099	0	0	0
T26	914799	0	0	0
T27	470748	0	0	0
T28	811128	0	0	0
T29	325767	0	0	0
T30	117089	0	0	0
T31	626292	0	0	0
T32	494258	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1791	0	0
T14	225240	10	0	0
T15	0	27	0	0
T16	0	13	0	0
T17	0	35	0	0
T18	0	30	0	0
T19	0	45	0	0
T20	0	18	0	0
T21	0	17	0	0
T22	0	8	0	0
T23	0	38	0	0
T24	231678	0	0	0
T25	25099	0	0	0
T26	914799	0	0	0
T27	470748	0	0	0
T28	811128	0	0	0
T29	325767	0	0	0
T30	117089	0	0	0
T31	626292	0	0	0
T32	494258	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2032	0	0
T14	225240	11	0	0
T15	0	30	0	0
T16	0	16	0	0
T17	0	33	0	0
T18	0	23	0	0
T19	0	41	0	0
T20	0	14	0	0
T21	0	25	0	0
T22	0	14	0	0
T23	0	42	0	0
T24	231678	0	0	0
T25	25099	0	0	0
T26	914799	0	0	0
T27	470748	0	0	0
T28	811128	0	0	0
T29	325767	0	0	0
T30	117089	0	0	0
T31	626292	0	0	0
T32	494258	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1949	0	0
T14	225240	6	0	0
T15	0	31	0	0
T16	0	15	0	0
T17	0	29	0	0
T18	0	13	0	0
T19	0	41	0	0
T20	0	17	0	0
T21	0	12	0	0
T22	0	24	0	0
T23	0	57	0	0
T24	231678	0	0	0
T25	25099	0	0	0
T26	914799	0	0	0
T27	470748	0	0	0
T28	811128	0	0	0
T29	325767	0	0	0
T30	117089	0	0	0
T31	626292	0	0	0
T32	494258	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1854	0	0
T14	225240	14	0	0
T15	0	23	0	0
T16	0	11	0	0
T17	0	43	0	0
T18	0	15	0	0
T19	0	22	0	0
T20	0	4	0	0
T21	0	10	0	0
T22	0	26	0	0
T23	0	36	0	0
T24	231678	0	0	0
T25	25099	0	0	0
T26	914799	0	0	0
T27	470748	0	0	0
T28	811128	0	0	0
T29	325767	0	0	0
T30	117089	0	0	0
T31	626292	0	0	0
T32	494258	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1759	0	0
T14	225240	9	0	0
T15	0	30	0	0
T16	0	7	0	0
T17	0	17	0	0
T18	0	17	0	0
T19	0	38	0	0
T20	0	13	0	0
T21	0	17	0	0
T22	0	3	0	0
T23	0	64	0	0
T24	231678	0	0	0
T25	25099	0	0	0
T26	914799	0	0	0
T27	470748	0	0	0
T28	811128	0	0	0
T29	325767	0	0	0
T30	117089	0	0	0
T31	626292	0	0	0
T32	494258	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1894	0	0
T14	225240	15	0	0
T15	0	22	0	0
T16	0	1	0	0
T17	0	36	0	0
T18	0	21	0	0
T19	0	43	0	0
T20	0	14	0	0
T21	0	9	0	0
T22	0	23	0	0
T23	0	41	0	0
T24	231678	0	0	0
T25	25099	0	0	0
T26	914799	0	0	0
T27	470748	0	0	0
T28	811128	0	0	0
T29	325767	0	0	0
T30	117089	0	0	0
T31	626292	0	0	0
T32	494258	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1736	0	0
T14	225240	13	0	0
T15	0	35	0	0
T16	0	8	0	0
T17	0	31	0	0
T18	0	21	0	0
T19	0	40	0	0
T20	0	16	0	0
T21	0	12	0	0
T22	0	22	0	0
T23	0	32	0	0
T24	231678	0	0	0
T25	25099	0	0	0
T26	914799	0	0	0
T27	470748	0	0	0
T28	811128	0	0	0
T29	325767	0	0	0
T30	117089	0	0	0
T31	626292	0	0	0
T32	494258	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1864	0	0
T14	225240	11	0	0
T15	0	52	0	0
T17	0	34	0	0
T18	0	14	0	0
T19	0	17	0	0
T20	0	17	0	0
T21	0	28	0	0
T22	0	24	0	0
T23	0	37	0	0
T24	231678	0	0	0
T25	25099	0	0	0
T26	914799	0	0	0
T27	470748	0	0	0
T28	811128	0	0	0
T29	325767	0	0	0
T30	117089	0	0	0
T31	626292	0	0	0
T32	494258	0	0	0
T33	0	12	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1699	0	0
T14	225240	2	0	0
T15	0	30	0	0
T16	0	10	0	0
T17	0	21	0	0
T18	0	21	0	0
T19	0	22	0	0
T20	0	21	0	0
T21	0	30	0	0
T22	0	19	0	0
T23	0	47	0	0
T24	231678	0	0	0
T25	25099	0	0	0
T26	914799	0	0	0
T27	470748	0	0	0
T28	811128	0	0	0
T29	325767	0	0	0
T30	117089	0	0	0
T31	626292	0	0	0
T32	494258	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1588	0	0
T14	225240	11	0	0
T15	0	43	0	0
T16	0	17	0	0
T17	0	47	0	0
T18	0	23	0	0
T19	0	32	0	0
T20	0	22	0	0
T21	0	23	0	0
T22	0	26	0	0
T23	0	43	0	0
T24	231678	0	0	0
T25	25099	0	0	0
T26	914799	0	0	0
T27	470748	0	0	0
T28	811128	0	0	0
T29	325767	0	0	0
T30	117089	0	0	0
T31	626292	0	0	0
T32	494258	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2096	0	0
T15	375808	21	0	0
T16	0	3	0	0
T17	0	34	0	0
T18	0	22	0	0
T19	0	30	0	0
T20	0	17	0	0
T21	0	16	0	0
T22	0	22	0	0
T23	0	46	0	0
T33	0	28	0	0
T34	181513	0	0	0
T35	40811	0	0	0
T36	562014	0	0	0
T37	326355	0	0	0
T38	585720	0	0	0
T39	136080	0	0	0
T40	439492	0	0	0
T41	599875	0	0	0
T42	144298	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1673	0	0
T14	225240	27	0	0
T15	0	32	0	0
T16	0	4	0	0
T17	0	37	0	0
T18	0	22	0	0
T19	0	35	0	0
T20	0	17	0	0
T21	0	22	0	0
T22	0	20	0	0
T23	0	48	0	0
T24	231678	0	0	0
T25	25099	0	0	0
T26	914799	0	0	0
T27	470748	0	0	0
T28	811128	0	0	0
T29	325767	0	0	0
T30	117089	0	0	0
T31	626292	0	0	0
T32	494258	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1683	0	0
T14	225240	4	0	0
T15	0	30	0	0
T16	0	5	0	0
T17	0	38	0	0
T18	0	13	0	0
T19	0	31	0	0
T20	0	4	0	0
T21	0	27	0	0
T22	0	22	0	0
T23	0	18	0	0
T24	231678	0	0	0
T25	25099	0	0	0
T26	914799	0	0	0
T27	470748	0	0	0
T28	811128	0	0	0
T29	325767	0	0	0
T30	117089	0	0	0
T31	626292	0	0	0
T32	494258	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1478	0	0
T14	225240	23	0	0
T15	0	51	0	0
T16	0	17	0	0
T17	0	25	0	0
T18	0	14	0	0
T19	0	53	0	0
T20	0	8	0	0
T21	0	17	0	0
T22	0	24	0	0
T23	0	21	0	0
T24	231678	0	0	0
T25	25099	0	0	0
T26	914799	0	0	0
T27	470748	0	0	0
T28	811128	0	0	0
T29	325767	0	0	0
T30	117089	0	0	0
T31	626292	0	0	0
T32	494258	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1739	0	0
T14	225240	17	0	0
T15	0	34	0	0
T16	0	29	0	0
T17	0	40	0	0
T18	0	22	0	0
T19	0	32	0	0
T20	0	19	0	0
T21	0	25	0	0
T22	0	28	0	0
T23	0	38	0	0
T24	231678	0	0	0
T25	25099	0	0	0
T26	914799	0	0	0
T27	470748	0	0	0
T28	811128	0	0	0
T29	325767	0	0	0
T30	117089	0	0	0
T31	626292	0	0	0
T32	494258	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2183	0	0
T14	225240	35	0	0
T15	0	58	0	0
T16	0	11	0	0
T17	0	24	0	0
T18	0	28	0	0
T19	0	49	0	0
T20	0	21	0	0
T21	0	40	0	0
T24	231678	0	0	0
T25	25099	0	0	0
T26	914799	0	0	0
T27	470748	0	0	0
T28	811128	0	0	0
T29	325767	0	0	0
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