Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1158976	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1137048

1

T1

223

T2

1413

T3

6345

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2022710	1			T1	320		T2	2520		T3	12088
values[0x0]	136386	1			T1	49		T2	162		T3	433
values[0x1]	136928	1			T1	59		T2	152		T3	395

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	929014	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1367010

1

T1

265

T2

1697

T3

7657

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7226	1			T2	3		T3	40		T4	31
valid_sources[0x01]	17723	1			T2	6		T3	45		T4	32
valid_sources[0x02]	7304	1			T2	2		T3	43		T4	46
valid_sources[0x03]	9287	1			T2	6		T3	54		T4	19
valid_sources[0x04]	11078	1			T2	20		T3	48		T4	37
valid_sources[0x05]	6462	1			T2	3		T3	50		T4	50
valid_sources[0x06]	6675	1			T2	4		T3	56		T4	29
valid_sources[0x07]	7420	1			T2	2		T3	50		T4	28
valid_sources[0x08]	6586	1			T2	7		T3	54		T4	37
valid_sources[0x09]	6904	1			T2	10		T3	57		T4	39
valid_sources[0x0a]	8346	1			T2	9		T3	44		T4	32
valid_sources[0x0b]	6618	1			T2	3		T3	47		T4	36
valid_sources[0x0c]	13388	1			T2	3		T3	48		T4	22
valid_sources[0x0d]	6598	1			T2	2		T3	42		T4	18
valid_sources[0x0e]	14022	1			T2	2		T3	49		T4	48
valid_sources[0x0f]	6564	1			T2	5		T3	58		T4	27
valid_sources[0x10]	7654	1			T2	20		T3	66		T4	28
valid_sources[0x11]	6739	1			T1	9		T2	2		T3	66
valid_sources[0x12]	6817	1			T2	8		T3	75		T4	25
valid_sources[0x13]	9373	1			T2	16		T3	33		T4	37
valid_sources[0x14]	7142	1			T2	3		T3	51		T4	44
valid_sources[0x15]	11135	1			T2	3		T3	57		T4	22
valid_sources[0x16]	13765	1			T2	3		T3	75		T4	26
valid_sources[0x17]	15245	1			T2	5		T3	40		T4	56
valid_sources[0x18]	7037	1			T2	23		T3	43		T4	34
valid_sources[0x19]	7223	1			T2	2		T3	54		T4	21
valid_sources[0x1a]	13085	1			T2	17		T3	43		T4	27
valid_sources[0x1b]	11982	1			T2	1		T3	52		T4	36
valid_sources[0x1c]	7001	1			T2	3		T3	59		T4	23
valid_sources[0x1d]	6550	1			T2	19		T3	67		T4	38
valid_sources[0x1e]	13993	1			T2	8		T3	48		T4	37
valid_sources[0x1f]	8463	1			T2	12		T3	47		T4	48
valid_sources[0x20]	7957	1			T2	980		T3	36		T4	35
valid_sources[0x21]	7298	1			T2	7		T3	44		T4	19
valid_sources[0x22]	16673	1			T2	3		T3	34		T4	37
valid_sources[0x23]	7231	1			T2	3		T3	36		T4	29
valid_sources[0x24]	12040	1			T2	7		T3	69		T4	26
valid_sources[0x25]	6257	1			T2	3		T3	42		T4	17
valid_sources[0x26]	6693	1			T2	4		T3	40		T4	44
valid_sources[0x27]	7095	1			T2	4		T3	42		T4	34
valid_sources[0x28]	6742	1			T1	15		T2	4		T3	38
valid_sources[0x29]	8250	1			T2	10		T3	35		T4	35
valid_sources[0x2a]	16193	1			T2	7		T3	64		T4	42
valid_sources[0x2b]	6731	1			T2	4		T3	44		T4	33
valid_sources[0x2c]	6760	1			T2	31		T3	69		T4	25
valid_sources[0x2d]	6935	1			T2	2		T3	39		T4	37
valid_sources[0x2e]	12075	1			T2	4		T3	49		T4	20
valid_sources[0x2f]	6556	1			T2	13		T3	40		T4	33
valid_sources[0x30]	6984	1			T2	7		T3	54		T4	32
valid_sources[0x31]	7442	1			T1	1		T2	8		T3	62
valid_sources[0x32]	19695	1			T2	6		T3	52		T4	48
valid_sources[0x33]	17525	1			T2	5		T3	42		T4	23
valid_sources[0x34]	6743	1			T2	7		T3	42		T4	22
valid_sources[0x35]	6791	1			T2	8		T3	49		T4	34
valid_sources[0x36]	6733	1			T2	4		T3	39		T4	38
valid_sources[0x37]	9408	1			T2	10		T3	27		T4	24
valid_sources[0x38]	11760	1			T2	4		T3	54		T4	31
valid_sources[0x39]	8157	1			T2	32		T3	33		T4	29
valid_sources[0x3a]	6648	1			T2	3		T3	79		T4	22
valid_sources[0x3b]	6568	1			T1	20		T2	4		T3	43
valid_sources[0x3c]	6893	1			T2	8		T3	66		T4	23
valid_sources[0x3d]	6281	1			T2	6		T3	60		T4	21
valid_sources[0x3e]	6479	1			T2	10		T3	54		T4	28
valid_sources[0x3f]	22323	1			T2	8		T3	43		T4	13
valid_sources[0x40]	7047	1			T2	7		T3	63		T4	34
valid_sources[0x41]	7275	1			T2	28		T3	61		T4	39
valid_sources[0x42]	7954	1			T2	7		T3	50		T4	32
valid_sources[0x43]	10517	1			T2	15		T3	48		T4	42
valid_sources[0x44]	7252	1			T2	6		T3	45		T4	23
valid_sources[0x45]	11570	1			T2	8		T3	53		T4	51
valid_sources[0x46]	7464	1			T2	6		T3	50		T4	29
valid_sources[0x47]	10832	1			T2	3		T3	51		T4	16
valid_sources[0x48]	7003	1			T2	3		T3	52		T4	21
valid_sources[0x49]	7989	1			T2	18		T3	67		T4	24
valid_sources[0x4a]	11346	1			T2	4		T3	47		T4	48
valid_sources[0x4b]	6393	1			T2	2		T3	60		T4	29
valid_sources[0x4c]	6645	1			T2	5		T3	56		T4	26
valid_sources[0x4d]	9494	1			T2	5		T3	48		T4	59
valid_sources[0x4e]	6784	1			T2	2		T3	68		T4	30
valid_sources[0x4f]	6645	1			T2	3		T3	69		T4	14
valid_sources[0x50]	6553	1			T2	3		T3	36		T4	38
valid_sources[0x51]	6507	1			T2	2		T3	43		T4	41
valid_sources[0x52]	6507	1			T2	1		T3	46		T4	29
valid_sources[0x53]	9248	1			T1	15		T2	4		T3	47
valid_sources[0x54]	11925	1			T1	1		T2	5		T3	47
valid_sources[0x55]	9355	1			T2	6		T3	43		T4	15
valid_sources[0x56]	10807	1			T2	2		T3	56		T4	29
valid_sources[0x57]	6390	1			T2	5		T3	42		T4	29
valid_sources[0x58]	10697	1			T2	4		T3	46		T4	49
valid_sources[0x59]	26362	1			T2	3		T3	45		T4	13
valid_sources[0x5a]	6221	1			T2	3		T3	47		T4	55
valid_sources[0x5b]	7964	1			T2	1		T3	53		T4	17
valid_sources[0x5c]	12418	1			T2	4		T3	73		T4	36
valid_sources[0x5d]	6655	1			T2	6		T3	45		T4	35
valid_sources[0x5e]	6914	1			T2	20		T3	53		T4	26
valid_sources[0x5f]	7664	1			T3	71		T4	44		T5	29
valid_sources[0x60]	8442	1			T2	3		T3	36		T4	13
valid_sources[0x61]	9533	1			T2	4		T3	48		T4	57
valid_sources[0x62]	10605	1			T1	121		T2	19		T3	48
valid_sources[0x63]	7128	1			T2	4		T3	43		T4	15
valid_sources[0x64]	6701	1			T2	2		T3	40		T4	47
valid_sources[0x65]	6418	1			T2	6		T3	32		T4	24
valid_sources[0x66]	6181	1			T2	3		T3	34		T4	47
valid_sources[0x67]	6558	1			T2	14		T3	54		T4	80
valid_sources[0x68]	10079	1			T2	10		T3	37		T4	59
valid_sources[0x69]	11399	1			T2	11		T3	48		T4	67
valid_sources[0x6a]	12600	1			T2	19		T3	60		T4	44
valid_sources[0x6b]	6311	1			T2	13		T3	56		T4	55
valid_sources[0x6c]	9891	1			T2	5		T3	58		T4	22
valid_sources[0x6d]	7815	1			T2	11		T3	55		T4	47
valid_sources[0x6e]	10573	1			T2	2		T3	45		T4	50
valid_sources[0x6f]	12533	1			T2	8		T3	44		T4	35
valid_sources[0x70]	10936	1			T2	2		T3	45		T4	41
valid_sources[0x71]	9497	1			T2	5		T3	98		T4	32
valid_sources[0x72]	6680	1			T2	4		T3	54		T4	31
valid_sources[0x73]	11560	1			T2	2		T3	66		T4	24
valid_sources[0x74]	6303	1			T2	7		T3	48		T4	29
valid_sources[0x75]	6851	1			T2	7		T3	53		T4	45
valid_sources[0x76]	7189	1			T2	5		T3	35		T4	29
valid_sources[0x77]	9444	1			T1	6		T2	3		T3	50
valid_sources[0x78]	6347	1			T2	2		T3	42		T4	40
valid_sources[0x79]	11396	1			T2	5		T3	59		T4	27
valid_sources[0x7a]	9376	1			T2	4		T3	45		T4	41
valid_sources[0x7b]	10718	1			T2	3		T3	52		T4	51
valid_sources[0x7c]	7542	1			T2	2		T3	67		T4	17
valid_sources[0x7d]	10713	1			T2	1		T3	37		T4	46
valid_sources[0x7e]	6918	1			T2	2		T3	40		T4	25
valid_sources[0x7f]	6931	1			T2	2		T3	43		T4	37
valid_sources[0x80]	6822	1			T2	6		T3	52		T4	33

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1008366

1

T1

152

T2

1260

T3

6026

values[0x0]

all_enables

biggest_size

74764

1

T1

36

T2

91

T3

205

values[0x1]

all_enables

biggest_size

53918

1

T1

35

T2

62

T3

114