Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	27297	1			T2	20		T3	23		T4	16
auto[PWRUP]	95	1			T6	2		T38	4		T39	1
auto[ONEST_0]	58	1			T6	1		T37	2		T40	1
auto[ONEST_021]	9	1			T40	1		T199	1		T200	1
auto[ONEST_1]	74	1			T37	3		T43	1		T41	1
auto[ONEST_DONE]	1	1			T201	1		-	-		-	-
auto[LP_0]	100	1			T6	1		T37	1		T40	1
auto[LP_021]	26	1			T6	1		T40	1		T43	1
auto[LP_1]	113	1			T6	3		T37	2		T40	1
auto[LP_EVAL]	51	1			T6	1		T38	2		T39	1
auto[LP_SLP]	422	1			T6	9		T37	5		T40	4
auto[LP_PWRUP]	26	1			T40	1		T38	1		T189	2
auto[NP_0]	117	1			T6	1		T37	1		T40	1
auto[NP_021]	34	1			T40	2		T38	2		T39	1
auto[NP_1]	136	1			T40	3		T38	1		T39	2
auto[NP_EVAL]	29	1			T38	2		T39	1		T43	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

4

1

T200

1

T202

1

T203

1

min

26809

1

T2

20

T3

23

T4

16

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	26810	1			T2	20		T3	23		T4	16
pow[0x1]	12	1			T204	1		T205	1		T206	1
pow[0x2]	14	1			T40	1		T38	1		T39	2
pow[0x3]	24	1			T37	1		T39	1		T43	1
pow[0x4]	44	1			T37	2		T40	1		T39	1
pow[0x5]	111	1			T6	2		T38	2		T39	2
pow[0x6]	209	1			T6	3		T37	2		T40	1
pow[0x7]	487	1			T6	6		T37	8		T40	8

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

160

1

T6

3

T37

1

T40

3

min

26420

1

T2

20

T3

23

T4

16

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	26420	1			T2	20		T3	23		T4	16
pow[0x2]	1	1			T207	1		-	-		-	-
pow[0x5]	3	1			T43	1		T67	1		T208	1
pow[0x7]	2	1			T209	1		T201	1		-	-
pow[0x8]	2	1			T37	1		T40	1		-	-
pow[0x9]	8	1			T37	1		T210	1		T211	1
pow[0xa]	15	1			T43	1		T41	1		T212	1
pow[0xb]	29	1			T6	1		T40	1		T41	1
pow[0xc]	54	1			T6	1		T37	1		T41	1
pow[0xd]	125	1			T37	4		T40	2		T38	4
pow[0xe]	252	1			T6	2		T37	1		T40	2
pow[0xf]	489	1			T6	9		T37	8		T40	6