Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.33	93.33	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	93.33	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.33	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	3	42	93.33

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	2	14	87.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2055	1			T1	10		T6	17		T8	4
auto[PWRUP]	141	1			T11	1		T37	1		T40	1
auto[ONEST_0]	77	1			T6	2		T37	1		T32	1
auto[ONEST_021]	12	1			T37	1		T43	1		T204	1
auto[ONEST_1]	77	1			T6	2		T39	3		T31	1
auto[ONEST_DONE]	2	1			T350	1		T351	1		-	-
auto[LP_0]	99	1			T11	1		T37	1		T40	1
auto[LP_021]	16	1			T37	1		T352	1		T353	1
auto[LP_1]	114	1			T37	1		T40	1		T38	2
auto[LP_EVAL]	40	1			T40	1		T31	1		T189	1
auto[LP_SLP]	460	1			T6	2		T37	5		T40	4
auto[LP_PWRUP]	32	1			T6	1		T37	1		T40	2
auto[NP_0]	172	1			T1	2		T6	2		T37	2
auto[NP_021]	36	1			T6	1		T40	1		T186	2
auto[NP_1]	168	1			T1	1		T6	1		T11	1
auto[NP_EVAL]	22	1			T189	1		T204	1		T352	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

10

1

T37

1

T43

1

T41

1

min

1764

1

T1

13

T6

4

T8

4

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1777	1			T1	13		T6	4		T8	4
pow[0x1]	7	1			T204	1		T206	1		T200	1
pow[0x2]	18	1			T38	2		T43	1		T212	1
pow[0x3]	25	1			T37	2		T43	1		T204	3
pow[0x4]	62	1			T6	1		T37	1		T40	2
pow[0x5]	92	1			T6	2		T37	1		T40	2
pow[0x6]	231	1			T37	3		T40	7		T38	5
pow[0x7]	425	1			T6	9		T37	8		T40	8

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

167

1

T6

2

T37

3

T40

2

min

1274

1

T1

11

T6

3

T8

4

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	2	14	87.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1286	1			T1	11		T6	3		T8	4
pow[0x1]	9	1			T1	1		T31	1		T99	1
pow[0x2]	18	1			T32	2		T34	1		T15	1
pow[0x3]	16	1			T1	1		T287	2		T267	1
pow[0x4]	9	1			T31	1		T13	1		T89	1
pow[0x6]	2	1			T353	1		T354	1		-	-
pow[0x8]	4	1			T41	1		T355	1		T81	1
pow[0x9]	7	1			T40	1		T199	1		T211	1
pow[0xa]	19	1			T38	1		T43	2		T41	1
pow[0xb]	30	1			T37	1		T189	1		T204	1
pow[0xc]	65	1			T40	2		T43	1		T41	3
pow[0xd]	114	1			T6	2		T40	3		T38	1
pow[0xe]	271	1			T6	4		T37	1		T40	5
pow[0xf]	502	1			T6	4		T37	6		T40	6