Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2394	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2288	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2094	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2243	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2225	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2128	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2226	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2242	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2280	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2145	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2374	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2223	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2361	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2391	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2058	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2456	0	0
adc_en_ctl_rd_A	2147483647	1759	0	0
adc_fsm_rst_rd_A	2147483647	1531	0	0
adc_intr_ctl_rd_A	2147483647	2195	0	0
adc_lp_sample_ctl_rd_A	2147483647	1656	0	0
adc_pd_ctl_rd_A	2147483647	2039	0	0
adc_sample_ctl_rd_A	2147483647	1426	0	0
adc_wakeup_ctl_rd_A	2147483647	1751	0	0
intr_enable_rd_A	2147483647	1995	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2394	0	0
T11	273001	46	0	0
T12	984654	0	0	0
T13	0	33	0	0
T14	0	13	0	0
T15	0	29	0	0
T16	0	34	0	0
T17	0	21	0	0
T18	0	25	0	0
T19	0	29	0	0
T20	0	30	0	0
T21	0	19	0	0
T22	508063	0	0	0
T23	472937	0	0	0
T24	967307	0	0	0
T25	419553	0	0	0
T26	552045	0	0	0
T27	348181	0	0	0
T28	413049	0	0	0
T29	232143	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2288	0	0
T11	273001	42	0	0
T12	984654	0	0	0
T13	0	41	0	0
T14	0	26	0	0
T15	0	19	0	0
T16	0	43	0	0
T17	0	9	0	0
T18	0	38	0	0
T19	0	10	0	0
T20	0	43	0	0
T21	0	20	0	0
T22	508063	0	0	0
T23	472937	0	0	0
T24	967307	0	0	0
T25	419553	0	0	0
T26	552045	0	0	0
T27	348181	0	0	0
T28	413049	0	0	0
T29	232143	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2094	0	0
T11	273001	18	0	0
T12	984654	0	0	0
T13	0	40	0	0
T14	0	15	0	0
T15	0	37	0	0
T16	0	22	0	0
T17	0	12	0	0
T18	0	45	0	0
T19	0	37	0	0
T20	0	37	0	0
T21	0	26	0	0
T22	508063	0	0	0
T23	472937	0	0	0
T24	967307	0	0	0
T25	419553	0	0	0
T26	552045	0	0	0
T27	348181	0	0	0
T28	413049	0	0	0
T29	232143	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2243	0	0
T11	273001	45	0	0
T12	984654	0	0	0
T13	0	41	0	0
T14	0	16	0	0
T15	0	14	0	0
T16	0	47	0	0
T17	0	11	0	0
T18	0	52	0	0
T19	0	15	0	0
T20	0	27	0	0
T21	0	25	0	0
T22	508063	0	0	0
T23	472937	0	0	0
T24	967307	0	0	0
T25	419553	0	0	0
T26	552045	0	0	0
T27	348181	0	0	0
T28	413049	0	0	0
T29	232143	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2225	0	0
T11	273001	16	0	0
T12	984654	0	0	0
T13	0	48	0	0
T14	0	22	0	0
T15	0	12	0	0
T16	0	34	0	0
T17	0	10	0	0
T18	0	41	0	0
T19	0	14	0	0
T20	0	43	0	0
T21	0	6	0	0
T22	508063	0	0	0
T23	472937	0	0	0
T24	967307	0	0	0
T25	419553	0	0	0
T26	552045	0	0	0
T27	348181	0	0	0
T28	413049	0	0	0
T29	232143	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2128	0	0
T11	273001	54	0	0
T12	984654	0	0	0
T13	0	61	0	0
T14	0	22	0	0
T15	0	20	0	0
T16	0	35	0	0
T17	0	24	0	0
T18	0	43	0	0
T19	0	18	0	0
T20	0	42	0	0
T21	0	23	0	0
T22	508063	0	0	0
T23	472937	0	0	0
T24	967307	0	0	0
T25	419553	0	0	0
T26	552045	0	0	0
T27	348181	0	0	0
T28	413049	0	0	0
T29	232143	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2226	0	0
T11	273001	31	0	0
T12	984654	0	0	0
T13	0	37	0	0
T14	0	31	0	0
T15	0	19	0	0
T16	0	24	0	0
T17	0	17	0	0
T18	0	45	0	0
T19	0	5	0	0
T20	0	36	0	0
T21	0	13	0	0
T22	508063	0	0	0
T23	472937	0	0	0
T24	967307	0	0	0
T25	419553	0	0	0
T26	552045	0	0	0
T27	348181	0	0	0
T28	413049	0	0	0
T29	232143	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2242	0	0
T11	273001	40	0	0
T12	984654	0	0	0
T13	0	43	0	0
T14	0	22	0	0
T15	0	17	0	0
T16	0	36	0	0
T17	0	12	0	0
T18	0	36	0	0
T19	0	20	0	0
T20	0	50	0	0
T21	0	13	0	0
T22	508063	0	0	0
T23	472937	0	0	0
T24	967307	0	0	0
T25	419553	0	0	0
T26	552045	0	0	0
T27	348181	0	0	0
T28	413049	0	0	0
T29	232143	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2280	0	0
T11	273001	21	0	0
T12	984654	0	0	0
T13	0	45	0	0
T14	0	18	0	0
T15	0	19	0	0
T16	0	32	0	0
T17	0	4	0	0
T18	0	37	0	0
T19	0	37	0	0
T20	0	53	0	0
T21	0	18	0	0
T22	508063	0	0	0
T23	472937	0	0	0
T24	967307	0	0	0
T25	419553	0	0	0
T26	552045	0	0	0
T27	348181	0	0	0
T28	413049	0	0	0
T29	232143	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2145	0	0
T11	273001	40	0	0
T12	984654	0	0	0
T13	0	37	0	0
T14	0	22	0	0
T15	0	23	0	0
T16	0	46	0	0
T17	0	14	0	0
T18	0	23	0	0
T19	0	24	0	0
T20	0	38	0	0
T21	0	15	0	0
T22	508063	0	0	0
T23	472937	0	0	0
T24	967307	0	0	0
T25	419553	0	0	0
T26	552045	0	0	0
T27	348181	0	0	0
T28	413049	0	0	0
T29	232143	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2374	0	0
T11	273001	33	0	0
T12	984654	0	0	0
T13	0	41	0	0
T14	0	13	0	0
T15	0	9	0	0
T16	0	40	0	0
T17	0	26	0	0
T18	0	47	0	0
T19	0	10	0	0
T20	0	35	0	0
T21	0	48	0	0
T22	508063	0	0	0
T23	472937	0	0	0
T24	967307	0	0	0
T25	419553	0	0	0
T26	552045	0	0	0
T27	348181	0	0	0
T28	413049	0	0	0
T29	232143	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2223	0	0
T11	273001	35	0	0
T12	984654	0	0	0
T13	0	47	0	0
T14	0	13	0	0
T15	0	29	0	0
T16	0	48	0	0
T17	0	10	0	0
T18	0	35	0	0
T19	0	6	0	0
T20	0	24	0	0
T21	0	21	0	0
T22	508063	0	0	0
T23	472937	0	0	0
T24	967307	0	0	0
T25	419553	0	0	0
T26	552045	0	0	0
T27	348181	0	0	0
T28	413049	0	0	0
T29	232143	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2361	0	0
T11	273001	39	0	0
T12	984654	0	0	0
T13	0	45	0	0
T14	0	15	0	0
T15	0	16	0	0
T16	0	36	0	0
T17	0	21	0	0
T18	0	40	0	0
T19	0	20	0	0
T20	0	29	0	0
T21	0	30	0	0
T22	508063	0	0	0
T23	472937	0	0	0
T24	967307	0	0	0
T25	419553	0	0	0
T26	552045	0	0	0
T27	348181	0	0	0
T28	413049	0	0	0
T29	232143	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2391	0	0
T11	273001	27	0	0
T12	984654	0	0	0
T13	0	24	0	0
T14	0	16	0	0
T15	0	17	0	0
T16	0	52	0	0
T17	0	13	0	0
T18	0	31	0	0
T19	0	30	0	0
T20	0	23	0	0
T21	0	22	0	0
T22	508063	0	0	0
T23	472937	0	0	0
T24	967307	0	0	0
T25	419553	0	0	0
T26	552045	0	0	0
T27	348181	0	0	0
T28	413049	0	0	0
T29	232143	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2058	0	0
T11	273001	29	0	0
T12	984654	0	0	0
T13	0	43	0	0
T14	0	18	0	0
T15	0	10	0	0
T16	0	43	0	0
T17	0	6	0	0
T18	0	42	0	0
T19	0	23	0	0
T20	0	43	0	0
T21	0	17	0	0
T22	508063	0	0	0
T23	472937	0	0	0
T24	967307	0	0	0
T25	419553	0	0	0
T26	552045	0	0	0
T27	348181	0	0	0
T28	413049	0	0	0
T29	232143	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2456	0	0
T11	273001	41	0	0
T12	984654	0	0	0
T13	0	48	0	0
T14	0	22	0	0
T15	0	16	0	0
T16	0	29	0	0
T17	0	27	0	0
T18	0	50	0	0
T19	0	35	0	0
T20	0	38	0	0
T21	0	25	0	0
T22	508063	0	0	0
T23	472937	0	0	0
T24	967307	0	0	0
T25	419553	0	0	0
T26	552045	0	0	0
T27	348181	0	0	0
T28	413049	0	0	0
T29	232143	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1759	0	0
T11	273001	45	0	0
T12	984654	0	0	0
T13	0	50	0	0
T14	0	13	0	0
T15	0	16	0	0
T16	0	40	0	0
T17	0	28	0	0
T18	0	40	0	0
T19	0	10	0	0
T20	0	30	0	0
T21	0	13	0	0
T22	508063	0	0	0
T23	472937	0	0	0
T24	967307	0	0	0
T25	419553	0	0	0
T26	552045	0	0	0
T27	348181	0	0	0
T28	413049	0	0	0
T29	232143	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1531	0	0
T11	273001	33	0	0
T12	984654	0	0	0
T13	0	38	0	0
T14	0	14	0	0
T15	0	16	0	0
T16	0	21	0	0
T17	0	12	0	0
T18	0	36	0	0
T19	0	17	0	0
T20	0	44	0	0
T21	0	31	0	0
T22	508063	0	0	0
T23	472937	0	0	0
T24	967307	0	0	0
T25	419553	0	0	0
T26	552045	0	0	0
T27	348181	0	0	0
T28	413049	0	0	0
T29	232143	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2195	0	0
T11	273001	22	0	0
T12	984654	0	0	0
T13	0	35	0	0
T14	0	19	0	0
T15	0	11	0	0
T16	0	29	0	0
T17	0	6	0	0
T18	0	54	0	0
T19	0	25	0	0
T20	0	34	0	0
T21	0	22	0	0
T22	508063	0	0	0
T23	472937	0	0	0
T24	967307	0	0	0
T25	419553	0	0	0
T26	552045	0	0	0
T27	348181	0	0	0
T28	413049	0	0	0
T29	232143	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1656	0	0
T11	273001	39	0	0
T12	984654	0	0	0
T13	0	31	0	0
T14	0	32	0	0
T15	0	27	0	0
T16	0	43	0	0
T17	0	21	0	0
T18	0	34	0	0
T19	0	8	0	0
T20	0	32	0	0
T21	0	12	0	0
T22	508063	0	0	0
T23	472937	0	0	0
T24	967307	0	0	0
T25	419553	0	0	0
T26	552045	0	0	0
T27	348181	0	0	0
T28	413049	0	0	0
T29	232143	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2039	0	0
T11	273001	56	0	0
T12	984654	0	0	0
T13	0	37	0	0
T14	0	19	0	0
T15	0	8	0	0
T16	0	34	0	0
T17	0	3	0	0
T18	0	50	0	0
T19	0	20	0	0
T20	0	44	0	0
T21	0	26	0	0
T22	508063	0	0	0
T23	472937	0	0	0
T24	967307	0	0	0
T25	419553	0	0	0
T26	552045	0	0	0
T27	348181	0	0	0
T28	413049	0	0	0
T29	232143	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1426	0	0
T11	273001	45	0	0
T12	984654	0	0	0
T13	0	39	0	0
T14	0	32	0	0
T15	0	30	0	0
T16	0	32	0	0
T17	0	22	0	0
T18	0	37	0	0
T19	0	29	0	0
T20	0	29	0	0
T21	0	15	0	0
T22	508063	0	0	0
T23	472937	0	0	0
T24	967307	0	0	0
T25	419553	0	0	0
T26	552045	0	0	0
T27	348181	0	0	0
T28	413049	0	0	0
T29	232143	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1751	0	0
T11	273001	41	0	0
T12	984654	0	0	0
T13	0	36	0	0
T14	0	18	0	0
T15	0	26	0	0
T16	0	48	0	0
T17	0	7	0	0
T18	0	51	0	0
T19	0	15	0	0
T20	0	40	0	0
T21	0	24	0	0
T22	508063	0	0	0
T23	472937	0	0	0
T24	967307	0	0	0
T25	419553	0	0	0
T26	552045	0	0	0
T27	348181	0	0	0
T28	413049	0	0	0
T29	232143	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1995	0	0
T8	168375	29	0	0
T9	50694	0	0	0
T10	389282	0	0	0
T11	273001	40	0	0
T12	984654	0	0	0
T13	0	77	0	0
T14	0	17	0	0
T15	0	32	0	0
T16	0	43	0	0
T17	0	15	0	0
T18	0	50	0	0
T19	0	17	0	0
T22	508063	0	0	0
T23	472937	0	0	0
T24	967307	0	0	0
T25	419553	0	0	0
T26	552045	0	0	0
T30	0	17	0	0