Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1139475	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1111473

1

T1

2086

T2

425

T3

1395

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1981739	1			T1	3956		T3	2460		T5	100
values[0x0]	134328	1			T1	127		T2	536		T3	151
values[0x1]	134881	1			T1	121		T2	547		T3	148

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	912099	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1338849

1

T1

2521

T2

531

T3

1666

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6548	1			T1	14		T2	5		T3	11
valid_sources[0x01]	7337	1			T1	4		T2	8		T3	9
valid_sources[0x02]	7470	1			T1	13		T2	5		T3	4
valid_sources[0x03]	8229	1			T1	15		T2	2		T3	10
valid_sources[0x04]	7033	1			T1	3		T2	1		T3	5
valid_sources[0x05]	10887	1			T1	12		T2	7		T3	13
valid_sources[0x06]	7059	1			T1	3		T2	3		T3	3
valid_sources[0x07]	7073	1			T1	6		T2	10		T3	1
valid_sources[0x08]	7234	1			T1	27		T2	1		T3	6
valid_sources[0x09]	7649	1			T1	21		T2	9		T3	4
valid_sources[0x0a]	6814	1			T1	28		T2	5		T3	4
valid_sources[0x0b]	7935	1			T1	25		T2	5		T3	16
valid_sources[0x0c]	9055	1			T1	16		T3	2		T6	54
valid_sources[0x0d]	7267	1			T1	11		T2	4		T3	2
valid_sources[0x0e]	11363	1			T1	14		T2	10		T3	6
valid_sources[0x0f]	6801	1			T1	22		T2	5		T3	6
valid_sources[0x10]	7588	1			T1	17		T2	3		T3	2
valid_sources[0x11]	6709	1			T1	12		T2	1		T3	10
valid_sources[0x12]	7178	1			T1	11		T2	6		T3	7
valid_sources[0x13]	6931	1			T1	22		T2	3		T3	4
valid_sources[0x14]	11333	1			T1	17		T2	1		T3	9
valid_sources[0x15]	8525	1			T1	24		T2	9		T3	13
valid_sources[0x16]	9213	1			T1	7		T2	7		T3	5
valid_sources[0x17]	14081	1			T1	8		T2	1		T3	9
valid_sources[0x18]	10833	1			T1	9		T2	5		T3	5
valid_sources[0x19]	6915	1			T1	16		T2	6		T3	5
valid_sources[0x1a]	7270	1			T1	11		T2	3		T3	8
valid_sources[0x1b]	7836	1			T1	15		T2	5		T3	6
valid_sources[0x1c]	7764	1			T1	3		T2	6		T3	5
valid_sources[0x1d]	11460	1			T1	11		T2	4		T3	4
valid_sources[0x1e]	7077	1			T1	25		T2	6		T3	11
valid_sources[0x1f]	7124	1			T1	8		T2	13		T3	80
valid_sources[0x20]	7268	1			T1	32		T3	7		T6	32
valid_sources[0x21]	19865	1			T1	3		T2	4		T3	9
valid_sources[0x22]	6670	1			T1	33		T2	3		T3	16
valid_sources[0x23]	7032	1			T1	10		T2	8		T3	3
valid_sources[0x24]	6734	1			T1	18		T2	4		T3	12
valid_sources[0x25]	7074	1			T1	16		T2	3		T3	10
valid_sources[0x26]	8164	1			T1	22		T2	10		T3	12
valid_sources[0x27]	10863	1			T1	16		T2	6		T3	5
valid_sources[0x28]	12090	1			T1	11		T2	3		T3	2
valid_sources[0x29]	6774	1			T1	19		T2	7		T3	5
valid_sources[0x2a]	6928	1			T1	9		T2	3		T3	9
valid_sources[0x2b]	11185	1			T1	7		T2	5		T3	13
valid_sources[0x2c]	6976	1			T1	13		T2	6		T3	6
valid_sources[0x2d]	11096	1			T1	8		T2	6		T3	4
valid_sources[0x2e]	7902	1			T1	25		T2	5		T3	11
valid_sources[0x2f]	11322	1			T1	13		T2	4		T3	8
valid_sources[0x30]	24158	1			T1	31		T2	5		T3	13
valid_sources[0x31]	6871	1			T1	14		T2	4		T3	5
valid_sources[0x32]	6934	1			T1	15		T2	6		T3	7
valid_sources[0x33]	7752	1			T1	35		T2	7		T3	10
valid_sources[0x34]	8677	1			T1	34		T2	7		T3	3
valid_sources[0x35]	7210	1			T1	19		T2	5		T3	5
valid_sources[0x36]	9914	1			T1	17		T2	2		T3	10
valid_sources[0x37]	6893	1			T1	16		T2	2		T3	4
valid_sources[0x38]	11072	1			T1	21		T2	3		T3	11
valid_sources[0x39]	20229	1			T1	21		T2	1		T3	10
valid_sources[0x3a]	7017	1			T1	19		T2	4		T3	3
valid_sources[0x3b]	7882	1			T1	18		T2	6		T3	92
valid_sources[0x3c]	6963	1			T1	21		T2	1		T3	5
valid_sources[0x3d]	7241	1			T1	13		T2	3		T3	3
valid_sources[0x3e]	12033	1			T1	23		T2	2		T3	6
valid_sources[0x3f]	18618	1			T1	10		T2	9		T3	9
valid_sources[0x40]	7311	1			T1	41		T2	3		T3	19
valid_sources[0x41]	11258	1			T1	5		T2	1		T3	3
valid_sources[0x42]	6782	1			T1	16		T2	4		T3	6
valid_sources[0x43]	6904	1			T1	18		T2	4		T3	4
valid_sources[0x44]	7308	1			T1	38		T2	2		T3	8
valid_sources[0x45]	6770	1			T1	16		T2	5		T3	7
valid_sources[0x46]	11665	1			T1	12		T2	4		T3	6
valid_sources[0x47]	7230	1			T1	5		T3	3		T5	3
valid_sources[0x48]	6981	1			T1	7		T2	8		T3	9
valid_sources[0x49]	11390	1			T1	7		T2	2		T3	8
valid_sources[0x4a]	7067	1			T1	36		T2	1		T3	14
valid_sources[0x4b]	6954	1			T1	9		T2	3		T3	7
valid_sources[0x4c]	11123	1			T1	16		T2	5		T3	7
valid_sources[0x4d]	7965	1			T1	28		T2	3		T3	148
valid_sources[0x4e]	7139	1			T1	14		T2	3		T3	3
valid_sources[0x4f]	7049	1			T1	13		T2	7		T3	8
valid_sources[0x50]	8152	1			T1	41		T2	13		T3	5
valid_sources[0x51]	7061	1			T1	27		T2	2		T3	5
valid_sources[0x52]	7306	1			T1	21		T2	2		T3	13
valid_sources[0x53]	6848	1			T1	16		T2	3		T3	5
valid_sources[0x54]	7794	1			T1	8		T2	10		T3	9
valid_sources[0x55]	6708	1			T1	17		T2	2		T3	13
valid_sources[0x56]	6811	1			T1	14		T2	1		T3	3
valid_sources[0x57]	7867	1			T1	4		T2	5		T3	7
valid_sources[0x58]	6593	1			T1	12		T2	6		T3	12
valid_sources[0x59]	6766	1			T1	15		T2	4		T3	6
valid_sources[0x5a]	11165	1			T1	10		T2	1		T3	6
valid_sources[0x5b]	7033	1			T1	18		T2	7		T3	9
valid_sources[0x5c]	15907	1			T1	25		T3	5		T6	24
valid_sources[0x5d]	12193	1			T1	6		T2	3		T3	6
valid_sources[0x5e]	8673	1			T1	10		T2	3		T3	4
valid_sources[0x5f]	7252	1			T1	6		T2	3		T3	6
valid_sources[0x60]	15006	1			T1	5		T2	1		T3	8
valid_sources[0x61]	7585	1			T1	17		T2	5		T3	3
valid_sources[0x62]	6876	1			T1	34		T2	4		T3	9
valid_sources[0x63]	7865	1			T1	10		T2	7		T3	3
valid_sources[0x64]	15315	1			T1	10		T2	3		T3	6
valid_sources[0x65]	7332	1			T1	7		T2	5		T3	4
valid_sources[0x66]	7163	1			T1	25		T2	8		T3	4
valid_sources[0x67]	6363	1			T1	13		T3	14		T6	25
valid_sources[0x68]	6832	1			T1	11		T2	3		T3	19
valid_sources[0x69]	6573	1			T1	14		T2	4		T3	11
valid_sources[0x6a]	9582	1			T1	4		T2	3		T3	21
valid_sources[0x6b]	11264	1			T1	10		T2	4		T3	5
valid_sources[0x6c]	7122	1			T1	6		T2	2		T3	6
valid_sources[0x6d]	13228	1			T1	33		T2	7		T3	3
valid_sources[0x6e]	6927	1			T1	10		T2	4		T3	5
valid_sources[0x6f]	7007	1			T1	16		T3	9		T5	2
valid_sources[0x70]	7098	1			T1	32		T2	2		T3	10
valid_sources[0x71]	8191	1			T1	26		T2	5		T3	5
valid_sources[0x72]	6810	1			T1	10		T2	8		T3	9
valid_sources[0x73]	11755	1			T1	9		T2	5		T3	4
valid_sources[0x74]	6921	1			T1	3		T2	6		T3	7
valid_sources[0x75]	6886	1			T1	9		T2	3		T3	5
valid_sources[0x76]	7416	1			T1	11		T2	4		T3	7
valid_sources[0x77]	11434	1			T1	15		T2	6		T3	2
valid_sources[0x78]	11030	1			T1	18		T2	3		T3	4
valid_sources[0x79]	10898	1			T1	31		T2	1		T3	8
valid_sources[0x7a]	16063	1			T1	6		T2	6		T3	2
valid_sources[0x7b]	11595	1			T1	33		T2	8		T3	11
valid_sources[0x7c]	6791	1			T1	15		T2	4		T3	1
valid_sources[0x7d]	6916	1			T1	9		T2	6		T3	3
valid_sources[0x7e]	7731	1			T1	18		T2	7		T3	10
valid_sources[0x7f]	11271	1			T1	21		T2	4		T3	14
valid_sources[0x80]	8235	1			T1	4		T2	9		T3	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

985834

1

T1

2000

T3

1242

T5

56

values[0x0]

all_enables

biggest_size

73065

1

T1

53

T2

252

T3

96

values[0x1]

all_enables

biggest_size

52574

1

T1

33

T2

173

T3

57