Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	26774	1			T1	9		T2	253		T3	19
auto[PWRUP]	92	1			T2	1		T10	1		T31	5
auto[ONEST_0]	54	1			T2	2		T10	1		T31	1
auto[ONEST_021]	14	1			T47	1		T190	2		T51	1
auto[ONEST_1]	65	1			T10	1		T31	1		T49	1
auto[ONEST_DONE]	7	1			T191	1		T192	1		T193	1
auto[LP_0]	112	1			T2	5		T10	1		T31	5
auto[LP_021]	25	1			T47	1		T194	2		T51	2
auto[LP_1]	113	1			T2	3		T10	1		T31	3
auto[LP_EVAL]	48	1			T49	1		T50	1		T47	1
auto[LP_SLP]	457	1			T2	7		T10	6		T31	8
auto[LP_PWRUP]	28	1			T31	1		T48	1		T195	1
auto[NP_0]	145	1			T2	1		T10	1		T31	3
auto[NP_021]	32	1			T31	2		T50	2		T47	1
auto[NP_1]	130	1			T2	4		T10	2		T31	2
auto[NP_EVAL]	26	1			T10	1		T49	2		T50	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

4

1

T196

1

T197

1

T38

1

min

26348

1

T1

9

T2

248

T3

19

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	26355	1			T1	9		T2	248		T3	19
pow[0x1]	6	1			T186	1		T198	2		T199	1
pow[0x2]	10	1			T174	1		T190	1		T195	1
pow[0x3]	27	1			T31	2		T47	1		T200	1
pow[0x4]	57	1			T2	1		T50	1		T47	4
pow[0x5]	107	1			T2	2		T10	1		T31	2
pow[0x6]	256	1			T2	3		T31	6		T50	3
pow[0x7]	425	1			T2	5		T10	5		T31	7

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

167

1

T2

1

T10

2

T31

4

min

25908

1

T1

9

T2

242

T3

19

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	25908	1			T1	9		T2	242		T3	19
pow[0x6]	1	1			T201	1		-	-		-	-
pow[0x7]	2	1			T202	1		T203	1		-	-
pow[0x8]	6	1			T50	1		T51	1		T204	1
pow[0x9]	5	1			T194	1		T205	1		T203	1
pow[0xa]	17	1			T206	1		T205	1		T88	1
pow[0xb]	28	1			T31	1		T49	1		T50	1
pow[0xc]	70	1			T2	1		T10	2		T49	2
pow[0xd]	123	1			T2	1		T10	1		T31	1
pow[0xe]	238	1			T2	4		T10	6		T31	6
pow[0xf]	517	1			T2	11		T10	4		T31	14