Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2100	1			T2	17		T5	2		T8	12
auto[PWRUP]	120	1			T2	1		T8	1		T10	1
auto[ONEST_0]	69	1			T2	1		T32	1		T47	3
auto[ONEST_021]	16	1			T2	1		T50	1		T186	1
auto[ONEST_1]	83	1			T2	1		T8	1		T16	1
auto[ONEST_DONE]	5	1			T47	1		T200	1		T196	1
auto[LP_0]	109	1			T10	1		T16	1		T31	3
auto[LP_021]	33	1			T2	1		T47	1		T48	1
auto[LP_1]	155	1			T2	1		T10	4		T49	2
auto[LP_EVAL]	43	1			T2	1		T186	1		T200	3
auto[LP_SLP]	480	1			T2	11		T10	4		T31	6
auto[LP_PWRUP]	34	1			T2	1		T49	1		T50	2
auto[NP_0]	167	1			T9	1		T10	1		T16	2
auto[NP_021]	38	1			T31	1		T49	2		T44	1
auto[NP_1]	180	1			T2	1		T9	1		T16	1
auto[NP_EVAL]	25	1			T9	1		T47	1		T130	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T174

1

T196

1

T19

1

min

1757

1

T2

13

T5

2

T8

14

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1774	1			T2	14		T5	2		T8	14
pow[0x1]	6	1			T10	1		T190	1		T38	1
pow[0x2]	21	1			T31	1		T47	2		T186	1
pow[0x3]	31	1			T2	1		T10	1		T49	1
pow[0x4]	55	1			T174	1		T186	1		T194	1
pow[0x5]	129	1			T2	3		T10	1		T31	1
pow[0x6]	266	1			T2	3		T10	4		T31	3
pow[0x7]	481	1			T2	7		T10	7		T31	6

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

184

1

T2

3

T10

2

T31

3

min

1232

1

T2

1

T5

2

T8

14

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1246	1			T2	1		T5	2		T8	14
pow[0x1]	8	1			T9	1		T16	2		T32	1
pow[0x2]	16	1			T40	1		T17	1		T18	1
pow[0x3]	7	1			T40	1		T18	1		T289	1
pow[0x4]	19	1			T9	1		T44	5		T130	2
pow[0x5]	2	1			T355	1		T356	1		-	-
pow[0x7]	2	1			T206	1		T357	1		-	-
pow[0x8]	6	1			T48	1		T194	1		T358	1
pow[0x9]	11	1			T2	1		T36	1		T195	1
pow[0xa]	19	1			T31	1		T50	1		T47	1
pow[0xb]	47	1			T2	1		T10	1		T186	1
pow[0xc]	70	1			T10	1		T31	1		T49	1
pow[0xd]	112	1			T2	1		T10	2		T31	3
pow[0xe]	254	1			T2	2		T10	5		T31	1
pow[0xf]	517	1			T2	4		T10	7		T31	6