Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.83	100.00	99.76		100.00	99.37	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	99.75	100.00	100.00		100.00	98.73	100.00
u_adc_ctrl_intr	99.00	100.00	96.00			100.00	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		63	63	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	213	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	8	8
63	8	8
72	1	1
73	1	1
74	1	1
75	1	1
83	1	1
86	1	1
87	1	1
88	1	1
89	1	1
104	8	8
107	8	8
117	8	8
121	8	8
137	1	1
138	1	1
140	1	1
141	1	1
145	1	1
213	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	293	293	100.00
Logical	293	293	100.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T8

 LINE       83
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T113
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T113
0	1	Covered	T1,T3,T113
1	0	Covered	T1,T3,T28

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T1,T7,T9
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T12
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T11
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T7,T9

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T3,T7,T11
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T11
0	1	Covered	T3,T7,T11
1	0	Covered	T3,T7,T11

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T7
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T7
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T3,T7,T9
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T11
0	1	Covered	T3,T7,T11
1	0	Covered	T3,T7,T9

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T9
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T114
0	1	Covered	T1,T3,T114
1	0	Covered	T1,T3,T9

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T7
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T1,T7,T9
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T12
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T11
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T7,T9

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T3,T7,T11
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T11
0	1	Covered	T3,T7,T11
1	0	Covered	T3,T7,T11

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T7
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T7
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T3,T7,T9
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T11
0	1	Covered	T3,T7,T11
1	0	Covered	T3,T7,T9

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T9
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T114
0	1	Covered	T1,T3,T114
1	0	Covered	T1,T3,T9

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T6,T7
1	1	0	Covered	T1,T3,T6
1	1	1	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T6
1	1	0	Covered	T3,T6,T7
1	1	1	Covered	T1,T3,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T6,T7
1	1	0	Covered	T1,T3,T6
1	1	1	Covered	T1,T3,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T6,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T6,T7
1	1	0	Covered	T3,T6,T7
1	1	1	Covered	T3,T6,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T6,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T6,T7

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T11,T12
1	1	0	Covered	T6,T7,T11
1	1	1	Covered	T6,T7,T11

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T11
0	1	Covered	T6,T7,T11
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T7,T11

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T11
0	1	Covered	T6,T7,T11
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T7,T11

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T6,T7
1	1	0	Covered	T3,T6,T7
1	1	1	Covered	T3,T6,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T6,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T6,T7

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T7,T12
1	1	0	Covered	T6,T7,T11
1	1	1	Covered	T6,T7,T11

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T11
0	1	Covered	T6,T7,T11
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T7,T11

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T11
0	1	Covered	T6,T7,T11
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T7,T11

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T6,T7
1	1	0	Covered	T3,T6,T7
1	1	1	Covered	T3,T6,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T6,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T6,T7

 LINE       121
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T6

 LINE       121
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T6

 LINE       121
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T6

 LINE       121
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T3,T6
1	1	Covered	T3,T6,T7

 LINE       121
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T11
1	0	Covered	T1,T3,T6
1	1	Covered	T6,T7,T11

 LINE       121
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T3,T6
1	1	Covered	T3,T6,T7

 LINE       121
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T11
1	0	Covered	T1,T3,T6
1	1	Covered	T6,T7,T11

 LINE       121
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T3,T6
1	1	Covered	T3,T6,T7

 LINE       140
 EXPRESSION (aon_fsm_trans | reg2hw_i.filter_status.trans.q)
             ------1------   ---------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T29
1	0	Covered	T12,T13,T29

 LINE       145
 EXPRESSION (((|(reg2hw_i.filter_status.match.q & reg2hw_i.adc_wakeup_ctl.match_en.q))) || (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q))
             -------------------------------------1------------------------------------    ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T29
1	0	Covered	T1,T9,T12

 LINE       145
 SUB-EXPRESSION (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q)
                 ---------------1--------------   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T12,T13
1	0	Covered	T30,T46,T56
1	1	Covered	T12,T13,T29

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	83	3	3	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	83	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T5,T8
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T113

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T7,T9

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T7,T9

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T7,T11

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T7,T11

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T7,T9

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T7,T9

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T9

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T9

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T6,T7

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T6,T7

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	32933536	32653222	0	0
gen_filter_match[0].MatchCheck00_A	32933536	9089482	0	0
gen_filter_match[0].MatchCheck01_A	32933536	2381621	0	0
gen_filter_match[0].MatchCheck10_A	32933536	2414177	0	0
gen_filter_match[0].MatchCheck11_A	32933536	18767942	0	0
gen_filter_match[1].MatchCheck00_A	32933536	11255267	0	0
gen_filter_match[1].MatchCheck01_A	32933536	1004963	0	0
gen_filter_match[1].MatchCheck10_A	32933536	1111807	0	0
gen_filter_match[1].MatchCheck11_A	32933536	19281185	0	0
gen_filter_match[2].MatchCheck00_A	32933536	11879335	0	0
gen_filter_match[2].MatchCheck01_A	32933536	595487	0	0
gen_filter_match[2].MatchCheck10_A	32933536	721194	0	0
gen_filter_match[2].MatchCheck11_A	32933536	19457206	0	0
gen_filter_match[3].MatchCheck00_A	32933536	12000416	0	0
gen_filter_match[3].MatchCheck01_A	32933536	211184	0	0
gen_filter_match[3].MatchCheck10_A	32933536	307957	0	0
gen_filter_match[3].MatchCheck11_A	32933536	20133665	0	0
gen_filter_match[4].MatchCheck00_A	32933536	11716620	0	0
gen_filter_match[4].MatchCheck01_A	32933536	31677	0	0
gen_filter_match[4].MatchCheck10_A	32933536	135031	0	0
gen_filter_match[4].MatchCheck11_A	32933536	20769894	0	0
gen_filter_match[5].MatchCheck00_A	32933536	12673760	0	0
gen_filter_match[5].MatchCheck01_A	32933536	10	0	0
gen_filter_match[5].MatchCheck10_A	32933536	76	0	0
gen_filter_match[5].MatchCheck11_A	32933536	19979376	0	0
gen_filter_match[6].MatchCheck00_A	32933536	11871907	0	0
gen_filter_match[6].MatchCheck01_A	32933536	102443	0	0
gen_filter_match[6].MatchCheck10_A	32933536	39301	0	0
gen_filter_match[6].MatchCheck11_A	32933536	20639571	0	0
gen_filter_match[7].MatchCheck00_A	32933536	11440885	0	0
gen_filter_match[7].MatchCheck01_A	32933536	247319	0	0
gen_filter_match[7].MatchCheck10_A	32933536	102814	0	0
gen_filter_match[7].MatchCheck11_A	32933536	20862204	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32933536	32653222	0	0
T1	32132	32034	0	0
T2	22189	19166	0	0
T3	96079	95990	0	0
T4	7401	7333	0	0
T5	1286	1093	0	0
T6	66015	65939	0	0
T7	100337	100243	0	0
T8	1269	789	0	0
T9	1440	1181	0	0
T15	71	13	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32933536	9089482	0	0
T1	32132	4	0	0
T2	22189	19000	0	0
T3	96079	32163	0	0
T4	7401	7333	0	0
T5	1286	1093	0	0
T6	66015	3	0	0
T7	100337	3	0	0
T8	1269	789	0	0
T9	1440	1181	0	0
T15	71	13	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32933536	2381621	0	0
T3	96079	63827	0	0
T4	7401	0	0	0
T5	1286	0	0	0
T6	66015	0	0	0
T7	100337	0	0	0
T8	1269	0	0	0
T9	1440	0	0	0
T10	18858	0	0	0
T11	32845	0	0	0
T15	71	0	0	0
T131	0	31985	0	0
T132	0	1	0	0
T133	0	65741	0	0
T134	0	31678	0	0
T135	0	33126	0	0
T136	0	32049	0	0
T137	0	32083	0	0
T138	0	42147	0	0
T139	0	33875	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32933536	2414177	0	0
T7	100337	66523	0	0
T8	1269	0	0	0
T9	1440	0	0	0
T10	18858	0	0	0
T11	32845	32766	0	0
T12	43062	0	0	0
T13	121270	0	0	0
T14	97060	0	0	0
T15	71	0	0	0
T16	0	279	0	0
T28	0	32758	0	0
T39	97195	0	0	0
T44	0	3519	0	0
T49	0	64772	0	0
T56	0	32788	0	0
T57	0	36015	0	0
T140	0	33507	0	0
T141	0	1	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32933536	18767942	0	0
T1	32132	32030	0	0
T2	22189	166	0	0
T3	96079	0	0	0
T4	7401	0	0	0
T5	1286	0	0	0
T6	66015	65936	0	0
T7	100337	33717	0	0
T8	1269	0	0	0
T9	1440	0	0	0
T10	0	382	0	0
T12	0	42967	0	0
T13	0	121215	0	0
T14	0	96964	0	0
T15	71	0	0	0
T39	0	97129	0	0
T43	0	98315	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32933536	11255267	0	0
T1	32132	4	0	0
T2	22189	19166	0	0
T3	96079	64556	0	0
T4	7401	7333	0	0
T5	1286	1093	0	0
T6	66015	3	0	0
T7	100337	66526	0	0
T8	1269	789	0	0
T9	1440	18	0	0
T15	71	13	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32933536	1004963	0	0
T3	96079	1	0	0
T4	7401	0	0	0
T5	1286	0	0	0
T6	66015	0	0	0
T7	100337	33717	0	0
T8	1269	0	0	0
T9	1440	0	0	0
T10	18858	0	0	0
T11	32845	0	0	0
T15	71	0	0	0
T114	0	32618	0	0
T134	0	1	0	0
T142	0	36918	0	0
T143	0	622	0	0
T144	0	32970	0	0
T145	0	31993	0	0
T146	0	32427	0	0
T147	0	168	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32933536	1111807	0	0
T3	96079	2	0	0
T4	7401	0	0	0
T5	1286	0	0	0
T6	66015	0	0	0
T7	100337	0	0	0
T8	1269	0	0	0
T9	1440	0	0	0
T10	18858	0	0	0
T11	32845	0	0	0
T15	71	0	0	0
T30	0	32597	0	0
T42	0	103	0	0
T109	0	32680	0	0
T113	0	33783	0	0
T132	0	1	0	0
T134	0	2	0	0
T141	0	1	0	0
T148	0	35195	0	0
T149	0	40514	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32933536	19281185	0	0
T1	32132	32030	0	0
T2	22189	0	0	0
T3	96079	31431	0	0
T4	7401	0	0	0
T5	1286	0	0	0
T6	66015	65936	0	0
T7	100337	0	0	0
T8	1269	0	0	0
T9	1440	1163	0	0
T12	0	42967	0	0
T13	0	121215	0	0
T14	0	96964	0	0
T15	71	0	0	0
T39	0	97129	0	0
T43	0	98315	0	0
T112	0	64643	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32933536	11879335	0	0
T1	32132	4	0	0
T2	22189	19166	0	0
T3	96079	63831	0	0
T4	7401	7333	0	0
T5	1286	1093	0	0
T6	66015	3	0	0
T7	100337	33720	0	0
T8	1269	789	0	0
T9	1440	18	0	0
T15	71	13	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32933536	595487	0	0
T1	32132	32030	0	0
T2	22189	0	0	0
T3	96079	0	0	0
T4	7401	0	0	0
T5	1286	0	0	0
T6	66015	0	0	0
T7	100337	0	0	0
T8	1269	0	0	0
T9	1440	0	0	0
T15	71	0	0	0
T30	0	1	0	0
T134	0	1	0	0
T145	0	32518	0	0
T150	0	38963	0	0
T151	0	33311	0	0
T152	0	1	0	0
T153	0	32432	0	0
T154	0	1	0	0
T155	0	36434	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32933536	721194	0	0
T3	96079	2	0	0
T4	7401	0	0	0
T5	1286	0	0	0
T6	66015	0	0	0
T7	100337	0	0	0
T8	1269	0	0	0
T9	1440	0	0	0
T10	18858	0	0	0
T11	32845	1	0	0
T15	71	0	0	0
T30	0	1	0	0
T114	0	32419	0	0
T134	0	1	0	0
T156	0	32715	0	0
T157	0	32922	0	0
T158	0	1	0	0
T159	0	1	0	0
T160	0	68483	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32933536	19457206	0	0
T3	96079	32157	0	0
T4	7401	0	0	0
T5	1286	0	0	0
T6	66015	65936	0	0
T7	100337	66523	0	0
T8	1269	0	0	0
T9	1440	1163	0	0
T10	18858	0	0	0
T11	32845	32765	0	0
T12	0	42967	0	0
T13	0	121215	0	0
T14	0	96964	0	0
T15	71	0	0	0
T39	0	97129	0	0
T43	0	98315	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32933536	12000416	0	0
T1	32132	32034	0	0
T2	22189	19166	0	0
T3	96079	63594	0	0
T4	7401	7333	0	0
T5	1286	1093	0	0
T6	66015	3	0	0
T7	100337	67183	0	0
T8	1269	789	0	0
T9	1440	18	0	0
T15	71	13	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32933536	211184	0	0
T3	96079	2	0	0
T4	7401	0	0	0
T5	1286	0	0	0
T6	66015	0	0	0
T7	100337	0	0	0
T8	1269	0	0	0
T9	1440	0	0	0
T10	18858	0	0	0
T11	32845	0	0	0
T15	71	0	0	0
T132	0	1	0	0
T134	0	1	0	0
T161	0	32510	0	0
T162	0	33140	0	0
T163	0	1	0	0
T164	0	3	0	0
T165	0	1	0	0
T166	0	36580	0	0
T167	0	38936	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32933536	307957	0	0
T3	96079	1	0	0
T4	7401	0	0	0
T5	1286	0	0	0
T6	66015	0	0	0
T7	100337	0	0	0
T8	1269	0	0	0
T9	1440	0	0	0
T10	18858	0	0	0
T11	32845	1	0	0
T15	71	0	0	0
T18	0	2	0	0
T30	0	1	0	0
T114	0	1	0	0
T132	0	2	0	0
T134	0	1	0	0
T158	0	1	0	0
T168	0	1	0	0
T169	0	32939	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32933536	20133665	0	0
T3	96079	32393	0	0
T4	7401	0	0	0
T5	1286	0	0	0
T6	66015	65936	0	0
T7	100337	33060	0	0
T8	1269	0	0	0
T9	1440	1163	0	0
T10	18858	0	0	0
T11	32845	32765	0	0
T12	0	42967	0	0
T13	0	121215	0	0
T14	0	96964	0	0
T15	71	0	0	0
T39	0	97129	0	0
T43	0	98315	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32933536	11716620	0	0
T1	32132	32034	0	0
T2	22189	19166	0	0
T3	96079	95990	0	0
T4	7401	7333	0	0
T5	1286	1093	0	0
T6	66015	3	0	0
T7	100337	67183	0	0
T8	1269	789	0	0
T9	1440	1181	0	0
T15	71	13	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32933536	31677	0	0
T132	106404	1	0	0
T133	98139	0	0	0
T134	101568	1	0	0
T135	67170	0	0	0
T136	64000	0	0	0
T148	69640	0	0	0
T149	72983	0	0	0
T152	0	2	0	0
T165	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0
T173	0	31669	0	0
T174	26111	0	0	0
T175	575	0	0	0
T176	1188	0	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32933536	135031	0	0
T11	32845	1	0	0
T12	43062	0	0	0
T13	121270	0	0	0
T14	97060	0	0	0
T17	0	1	0	0
T39	97195	0	0	0
T43	98380	0	0	0
T73	94	0	0	0
T112	64734	0	0	0
T113	33854	0	0	0
T114	65099	0	0	0
T132	0	1	0	0
T134	0	1	0	0
T141	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T168	0	1	0	0
T177	0	1	0	0
T178	0	2	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32933536	20769894	0	0
T6	66015	65936	0	0
T7	100337	33060	0	0
T8	1269	0	0	0
T9	1440	0	0	0
T10	18858	0	0	0
T11	32845	32765	0	0
T12	43062	42967	0	0
T13	121270	121215	0	0
T14	97060	96964	0	0
T15	71	0	0	0
T39	0	97129	0	0
T43	0	98315	0	0
T112	0	64643	0	0
T113	0	33783	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32933536	12673760	0	0
T1	32132	32034	0	0
T2	22189	19166	0	0
T3	96079	32161	0	0
T4	7401	7333	0	0
T5	1286	1093	0	0
T6	66015	3	0	0
T7	100337	66780	0	0
T8	1269	789	0	0
T9	1440	1181	0	0
T15	71	13	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32933536	10	0	0
T3	96079	1	0	0
T4	7401	0	0	0
T5	1286	0	0	0
T6	66015	0	0	0
T7	100337	0	0	0
T8	1269	0	0	0
T9	1440	0	0	0
T10	18858	0	0	0
T11	32845	0	0	0
T15	71	0	0	0
T132	0	1	0	0
T141	0	1	0	0
T152	0	1	0	0
T165	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32933536	76	0	0
T3	96079	1	0	0
T4	7401	0	0	0
T5	1286	0	0	0
T6	66015	0	0	0
T7	100337	0	0	0
T8	1269	0	0	0
T9	1440	0	0	0
T10	18858	0	0	0
T11	32845	0	0	0
T15	71	0	0	0
T17	0	1	0	0
T132	0	1	0	0
T134	0	1	0	0
T141	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T168	0	1	0	0
T177	0	1	0	0
T181	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32933536	19979376	0	0
T3	96079	63827	0	0
T4	7401	0	0	0
T5	1286	0	0	0
T6	66015	65936	0	0
T7	100337	33463	0	0
T8	1269	0	0	0
T9	1440	0	0	0
T10	18858	0	0	0
T11	32845	0	0	0
T12	0	42967	0	0
T13	0	121215	0	0
T14	0	96964	0	0
T15	71	0	0	0
T39	0	97129	0	0
T43	0	98315	0	0
T112	0	64643	0	0
T113	0	33783	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32933536	11871907	0	0
T1	32132	32034	0	0
T2	22189	19166	0	0
T3	96079	95990	0	0
T4	7401	7333	0	0
T5	1286	1093	0	0
T6	66015	3	0	0
T7	100337	66780	0	0
T8	1269	789	0	0
T9	1440	1181	0	0
T15	71	13	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32933536	102443	0	0
T134	101568	1	0	0
T135	67170	0	0	0
T136	64000	0	0	0
T137	65114	0	0	0
T148	69640	0	0	0
T149	72983	0	0	0
T154	0	1	0	0
T165	0	1	0	0
T167	0	1	0	0
T172	0	1	0	0
T174	26111	0	0	0
T175	575	0	0	0
T176	1188	0	0	0
T179	0	1	0	0
T182	0	1	0	0
T183	0	36298	0	0
T184	0	33724	0	0
T185	0	2	0	0
T186	16976	0	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32933536	39301	0	0
T11	32845	1	0	0
T12	43062	0	0	0
T13	121270	0	0	0
T14	97060	0	0	0
T17	0	1	0	0
T18	0	3	0	0
T30	0	1	0	0
T39	97195	0	0	0
T43	98380	0	0	0
T73	94	0	0	0
T103	0	1	0	0
T112	64734	0	0	0
T113	33854	0	0	0
T114	65099	0	0	0
T132	0	1	0	0
T134	0	1	0	0
T158	0	1	0	0
T168	0	1	0	0
T181	0	1	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32933536	20639571	0	0
T6	66015	65936	0	0
T7	100337	33463	0	0
T8	1269	0	0	0
T9	1440	0	0	0
T10	18858	0	0	0
T11	32845	32765	0	0
T12	43062	42967	0	0
T13	121270	121215	0	0
T14	97060	96964	0	0
T15	71	0	0	0
T39	0	97129	0	0
T43	0	98315	0	0
T112	0	64643	0	0
T114	0	65036	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32933536	11440885	0	0
T1	32132	32034	0	0
T2	22189	19166	0	0
T3	96079	32160	0	0
T4	7401	7333	0	0
T5	1286	1093	0	0
T6	66015	3	0	0
T7	100337	3	0	0
T8	1269	789	0	0
T9	1440	18	0	0
T15	71	13	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32933536	247319	0	0
T3	96079	2	0	0
T4	7401	0	0	0
T5	1286	0	0	0
T6	66015	0	0	0
T7	100337	0	0	0
T8	1269	0	0	0
T9	1440	1163	0	0
T10	18858	0	0	0
T11	32845	0	0	0
T15	71	0	0	0
T18	0	1928	0	0
T132	0	36098	0	0
T152	0	1	0	0
T164	0	3	0	0
T170	0	1	0	0
T187	0	31946	0	0
T188	0	1610	0	0
T189	0	31663	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32933536	102814	0	0
T3	96079	2	0	0
T4	7401	0	0	0
T5	1286	0	0	0
T6	66015	0	0	0
T7	100337	0	0	0
T8	1269	0	0	0
T9	1440	0	0	0
T10	18858	0	0	0
T11	32845	0	0	0
T15	71	0	0	0
T17	0	1	0	0
T30	0	1	0	0
T114	0	1	0	0
T134	0	1	0	0
T141	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T168	0	1	0	0
T181	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32933536	20862204	0	0
T3	96079	63826	0	0
T4	7401	0	0	0
T5	1286	0	0	0
T6	66015	65936	0	0
T7	100337	100240	0	0
T8	1269	0	0	0
T9	1440	0	0	0
T10	18858	0	0	0
T11	32845	0	0	0
T12	0	42967	0	0
T13	0	121215	0	0
T14	0	96964	0	0
T15	71	0	0	0
T39	0	97129	0	0
T43	0	98315	0	0
T112	0	64643	0	0
T113	0	33783	0	0