Unified Coverage Report :: Module :: prim_reg_cdc_arb

Module : prim_reg_cdc_arb

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.04	100.00	96.51			95.65	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb	77.58	95.65	78.95			85.71	50.00
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb	83.73	90.00	66.67			78.26	100.00
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb	83.73	90.00	66.67			78.26	100.00
tb.dut.u_reg.u_filter_status_cdc.u_arb	97.72	100.00	95.24			95.65	100.00
tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb	100.00	100.00	100.00
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb	100.00	100.00	100.00

Line Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=2,ResetVal=0,DstWrReq=0 + DataWidth=32,ResetVal,DstWrReq=0 + DataWidth=8,ResetVal=4,DstWrReq=0 + DataWidth=16,ResetVal=155,DstWrReq=0 + DataWidth=1,ResetVal=0,DstWrReq=0 + DataWidth=9,ResetVal=0,DstWrReq=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	299	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
283	1	1
284	1	1
299		unreachable

---

Line Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=28,ResetVal=0,DstWrReq=1 + DataWidth=9,ResetVal=0,DstWrReq=1 + DataWidth=5,ResetVal=0,DstWrReq=1 )
Line Coverage for Module self-instances :

SCORE	LINE
83.73	90.00

tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb

SCORE	LINE
83.73	90.00

tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb

SCORE	LINE
97.72	100.00

tb.dut.u_reg.u_filter_status_cdc.u_arb

SCORE	LINE
77.58	95.65

tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb

	Line No.	Total	Covered	Percent
TOTAL		50	50	100.00
CONT_ASSIGN	100	1	1	100.00
ALWAYS	111	3	3	100.00
ALWAYS	121	6	6	100.00
CONT_ASSIGN	135	1	1	100.00
ALWAYS	139	6	6	100.00
ALWAYS	155	10	10	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	187	19	19	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	244	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
111	1	1
112	1	1
114	1	1
121	1	1
122	1	1
123	1	1
128	1	1
129	1	1
132	1	1
			MISSING_ELSE
135	1	1
139	1	1
140	1	1
141	1	1
142	1	1
143	1	1
144	1	1
			MISSING_ELSE
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
			MISSING_ELSE
183	1	1
187	1	1
188	1	1
192	1	1
193	1	1
195	1	1
197	1	1
199	1	1
200	1	1
202	1	1
203	1	1
204	1	1
205	1	1
206	1	1
207	1	1
210	1	1
211	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
			MISSING_ELSE
228	1	1
243	1	1
244	1	1

---

Cond Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=2,ResetVal=0,DstWrReq=0 + DataWidth=32,ResetVal,DstWrReq=0 + DataWidth=8,ResetVal=4,DstWrReq=0 + DataWidth=16,ResetVal=155,DstWrReq=0 + DataWidth=1,ResetVal=0,DstWrReq=0 + DataWidth=9,ResetVal=0,DstWrReq=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=28,ResetVal=0,DstWrReq=1 + DataWidth=9,ResetVal=0,DstWrReq=1 + DataWidth=5,ResetVal=0,DstWrReq=1 )
Cond Coverage for Module self-instances :

SCORE	COND
83.73	66.67

tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb

SCORE	COND
83.73	66.67

tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb

SCORE	COND
97.72	95.24

tb.dut.u_reg.u_filter_status_cdc.u_arb

SCORE	COND
77.58	78.95

tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb

	Total	Covered	Percent
Conditions	43	40	93.02
Logical	43	40	93.02
Non-Logical	0	0
Event	0	0

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       123
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T53,T54
1	1	Covered	T55,T52,T53

 LINE       129
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T1,T3,T6
1	1	1	Covered	T55,T52,T53

 LINE       135
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T6
1	0	Covered	T55,T52,T53

 LINE       157
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       159
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T53,T54
1	1	Covered	T1,T3,T6

 LINE       161
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       183
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T55,T52,T53
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       207
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       228
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T6
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       243
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       243
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc_arb

	Line No.	Total	Covered	Percent
Branches		23	22	95.65
IF	111	2	2	100.00
IF	121	4	4	100.00
IF	139	4	4	100.00
IF	155	6	6	100.00
CASE	197	7	6	85.71

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	121	if ((!rst_dst_ni))
-2-:	123	if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d))
-3-:	129	if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T55,T52,T53
0	0	1	Covered	T55,T52,T53
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	139	if ((!rst_dst_ni))
-2-:	141	if (gen_wr_req.dst_lat_d)
-3-:	143	if (gen_wr_req.dst_lat_q)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	if ((!rst_dst_ni))
-2-:	157	if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack))
-3-:	159	if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d))
-4-:	161	if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d))
-5-:	163	if (gen_wr_req.dst_lat_q)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	Covered	T1,T3,T6
0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	1	Covered	T1,T3,T6
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	197	case (gen_wr_req.state_q)
-2-:	200	if (gen_wr_req.dst_req)
-3-:	204	if (dst_update)
-4-:	207	if ((dst_qs_o != dst_qs_i))
-5-:	217	if (gen_wr_req.dst_update_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StIdle	1	-	-	-	Covered	T1,T3,T6
StIdle	0	1	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	Covered	T1,T3,T6
StIdle	0	0	0	-	Covered	T1,T2,T3
StWait	-	-	-	1	Covered	T1,T2,T3
StWait	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	Not Covered

---

Assert Coverage for Module : prim_reg_cdc_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wr_req.DstUpdateReqCheck_A	132025248	1227416	0	3680
gen_wr_req.HwIdSelCheck_A	132025248	4348479	0	0

gen_wr_req.DstUpdateReqCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132025248	1227416	0	3680
T1	96396	1367	0	3
T2	66567	508	0	3
T3	288237	4132	0	3
T4	22203	96	0	3
T5	3858	59	0	3
T6	198045	2859	0	3
T7	301011	4245	0	3
T8	3807	38	0	3
T9	4320	6	0	3
T10	0	380	0	0
T11	0	17	0	0
T12	0	28	0	0
T13	0	83	0	0
T14	0	46	0	0
T15	213	0	0	3

gen_wr_req.HwIdSelCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132025248	4348479	0	0
T1	128528	4661	0	0
T2	88756	1877	0	0
T3	384316	13991	0	0
T4	29604	386	0	0
T5	5144	179	0	0
T6	264060	9645	0	0
T7	401348	14532	0	0
T8	5076	121	0	0
T9	5760	31	0	0
T10	0	1403	0	0
T11	0	17	0	0
T12	0	28	0	0
T13	0	83	0	0
T14	0	46	0	0
T15	284	0	0	0