Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1473	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1489	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1459	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1414	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1501	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1481	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1466	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1469	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1384	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1519	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1280	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1433	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1411	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1424	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1483	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1398	0	0
adc_en_ctl_rd_A	2147483647	1259	0	0
adc_fsm_rst_rd_A	2147483647	1084	0	0
adc_intr_ctl_rd_A	2147483647	1282	0	0
adc_lp_sample_ctl_rd_A	2147483647	1104	0	0
adc_pd_ctl_rd_A	2147483647	1208	0	0
adc_sample_ctl_rd_A	2147483647	1021	0	0
adc_wakeup_ctl_rd_A	2147483647	1108	0	0
intr_enable_rd_A	2147483647	1452	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1473	0	0
T16	452012	10	0	0
T17	0	31	0	0
T18	0	11	0	0
T19	0	28	0	0
T20	0	23	0	0
T21	0	20	0	0
T22	0	41	0	0
T23	0	10	0	0
T24	0	29	0	0
T25	0	43	0	0
T26	43058	0	0	0
T27	5082	0	0	0
T28	804922	0	0	0
T29	345631	0	0	0
T30	677548	0	0	0
T31	114353	0	0	0
T32	496053	0	0	0
T33	284040	0	0	0
T34	193708	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1489	0	0
T16	452012	12	0	0
T17	0	32	0	0
T18	0	25	0	0
T19	0	32	0	0
T20	0	10	0	0
T21	0	27	0	0
T22	0	44	0	0
T23	0	17	0	0
T24	0	31	0	0
T26	43058	0	0	0
T27	5082	0	0	0
T28	804922	0	0	0
T29	345631	0	0	0
T30	677548	0	0	0
T31	114353	0	0	0
T32	496053	0	0	0
T33	284040	0	0	0
T34	193708	0	0	0
T35	0	14	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1459	0	0
T16	452012	24	0	0
T17	0	20	0	0
T18	0	9	0	0
T19	0	20	0	0
T20	0	11	0	0
T21	0	14	0	0
T22	0	52	0	0
T23	0	9	0	0
T24	0	43	0	0
T26	43058	0	0	0
T27	5082	0	0	0
T28	804922	0	0	0
T29	345631	0	0	0
T30	677548	0	0	0
T31	114353	0	0	0
T32	496053	0	0	0
T33	284040	0	0	0
T34	193708	0	0	0
T35	0	10	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1414	0	0
T16	452012	19	0	0
T17	0	10	0	0
T18	0	14	0	0
T19	0	18	0	0
T20	0	1	0	0
T21	0	13	0	0
T22	0	30	0	0
T23	0	20	0	0
T24	0	38	0	0
T26	43058	0	0	0
T27	5082	0	0	0
T28	804922	0	0	0
T29	345631	0	0	0
T30	677548	0	0	0
T31	114353	0	0	0
T32	496053	0	0	0
T33	284040	0	0	0
T34	193708	0	0	0
T35	0	6	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1501	0	0
T16	452012	21	0	0
T17	0	29	0	0
T18	0	4	0	0
T19	0	31	0	0
T20	0	14	0	0
T21	0	21	0	0
T22	0	44	0	0
T23	0	10	0	0
T24	0	29	0	0
T26	43058	0	0	0
T27	5082	0	0	0
T28	804922	0	0	0
T29	345631	0	0	0
T30	677548	0	0	0
T31	114353	0	0	0
T32	496053	0	0	0
T33	284040	0	0	0
T34	193708	0	0	0
T35	0	3	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1481	0	0
T16	452012	13	0	0
T17	0	6	0	0
T18	0	10	0	0
T19	0	34	0	0
T20	0	5	0	0
T21	0	25	0	0
T22	0	47	0	0
T23	0	13	0	0
T24	0	41	0	0
T26	43058	0	0	0
T27	5082	0	0	0
T28	804922	0	0	0
T29	345631	0	0	0
T30	677548	0	0	0
T31	114353	0	0	0
T32	496053	0	0	0
T33	284040	0	0	0
T34	193708	0	0	0
T35	0	1	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1466	0	0
T16	452012	20	0	0
T17	0	30	0	0
T18	0	10	0	0
T19	0	20	0	0
T20	0	16	0	0
T21	0	18	0	0
T22	0	40	0	0
T23	0	2	0	0
T24	0	48	0	0
T26	43058	0	0	0
T27	5082	0	0	0
T28	804922	0	0	0
T29	345631	0	0	0
T30	677548	0	0	0
T31	114353	0	0	0
T32	496053	0	0	0
T33	284040	0	0	0
T34	193708	0	0	0
T35	0	22	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1469	0	0
T16	452012	20	0	0
T17	0	18	0	0
T18	0	8	0	0
T19	0	31	0	0
T20	0	24	0	0
T21	0	11	0	0
T22	0	41	0	0
T23	0	15	0	0
T24	0	35	0	0
T26	43058	0	0	0
T27	5082	0	0	0
T28	804922	0	0	0
T29	345631	0	0	0
T30	677548	0	0	0
T31	114353	0	0	0
T32	496053	0	0	0
T33	284040	0	0	0
T34	193708	0	0	0
T35	0	14	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1384	0	0
T16	452012	19	0	0
T17	0	18	0	0
T18	0	5	0	0
T19	0	22	0	0
T20	0	1	0	0
T21	0	12	0	0
T22	0	45	0	0
T23	0	9	0	0
T24	0	36	0	0
T26	43058	0	0	0
T27	5082	0	0	0
T28	804922	0	0	0
T29	345631	0	0	0
T30	677548	0	0	0
T31	114353	0	0	0
T32	496053	0	0	0
T33	284040	0	0	0
T34	193708	0	0	0
T35	0	7	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1519	0	0
T16	452012	18	0	0
T17	0	21	0	0
T18	0	8	0	0
T19	0	27	0	0
T20	0	9	0	0
T21	0	19	0	0
T22	0	45	0	0
T23	0	11	0	0
T24	0	31	0	0
T26	43058	0	0	0
T27	5082	0	0	0
T28	804922	0	0	0
T29	345631	0	0	0
T30	677548	0	0	0
T31	114353	0	0	0
T32	496053	0	0	0
T33	284040	0	0	0
T34	193708	0	0	0
T35	0	4	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1280	0	0
T16	452012	16	0	0
T17	0	17	0	0
T18	0	14	0	0
T19	0	31	0	0
T20	0	7	0	0
T21	0	16	0	0
T22	0	48	0	0
T23	0	9	0	0
T24	0	31	0	0
T26	43058	0	0	0
T27	5082	0	0	0
T28	804922	0	0	0
T29	345631	0	0	0
T30	677548	0	0	0
T31	114353	0	0	0
T32	496053	0	0	0
T33	284040	0	0	0
T34	193708	0	0	0
T35	0	5	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1433	0	0
T16	452012	21	0	0
T17	0	20	0	0
T18	0	1	0	0
T19	0	33	0	0
T20	0	6	0	0
T21	0	25	0	0
T22	0	35	0	0
T23	0	14	0	0
T24	0	36	0	0
T26	43058	0	0	0
T27	5082	0	0	0
T28	804922	0	0	0
T29	345631	0	0	0
T30	677548	0	0	0
T31	114353	0	0	0
T32	496053	0	0	0
T33	284040	0	0	0
T34	193708	0	0	0
T35	0	18	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1411	0	0
T16	452012	19	0	0
T17	0	12	0	0
T18	0	8	0	0
T19	0	22	0	0
T20	0	10	0	0
T21	0	18	0	0
T22	0	34	0	0
T23	0	15	0	0
T24	0	51	0	0
T26	43058	0	0	0
T27	5082	0	0	0
T28	804922	0	0	0
T29	345631	0	0	0
T30	677548	0	0	0
T31	114353	0	0	0
T32	496053	0	0	0
T33	284040	0	0	0
T34	193708	0	0	0
T35	0	8	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1424	0	0
T16	452012	17	0	0
T17	0	25	0	0
T18	0	17	0	0
T19	0	23	0	0
T20	0	7	0	0
T21	0	14	0	0
T22	0	47	0	0
T23	0	19	0	0
T24	0	33	0	0
T26	43058	0	0	0
T27	5082	0	0	0
T28	804922	0	0	0
T29	345631	0	0	0
T30	677548	0	0	0
T31	114353	0	0	0
T32	496053	0	0	0
T33	284040	0	0	0
T34	193708	0	0	0
T35	0	20	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1483	0	0
T16	452012	24	0	0
T17	0	14	0	0
T18	0	16	0	0
T19	0	27	0	0
T20	0	5	0	0
T21	0	27	0	0
T22	0	43	0	0
T23	0	5	0	0
T24	0	47	0	0
T26	43058	0	0	0
T27	5082	0	0	0
T28	804922	0	0	0
T29	345631	0	0	0
T30	677548	0	0	0
T31	114353	0	0	0
T32	496053	0	0	0
T33	284040	0	0	0
T34	193708	0	0	0
T35	0	21	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1398	0	0
T16	452012	12	0	0
T17	0	23	0	0
T18	0	8	0	0
T19	0	32	0	0
T20	0	12	0	0
T21	0	23	0	0
T22	0	44	0	0
T23	0	4	0	0
T24	0	32	0	0
T26	43058	0	0	0
T27	5082	0	0	0
T28	804922	0	0	0
T29	345631	0	0	0
T30	677548	0	0	0
T31	114353	0	0	0
T32	496053	0	0	0
T33	284040	0	0	0
T34	193708	0	0	0
T35	0	20	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1259	0	0
T16	452012	22	0	0
T17	0	11	0	0
T18	0	8	0	0
T19	0	20	0	0
T20	0	5	0	0
T21	0	14	0	0
T22	0	32	0	0
T23	0	14	0	0
T24	0	46	0	0
T26	43058	0	0	0
T27	5082	0	0	0
T28	804922	0	0	0
T29	345631	0	0	0
T30	677548	0	0	0
T31	114353	0	0	0
T32	496053	0	0	0
T33	284040	0	0	0
T34	193708	0	0	0
T35	0	7	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1084	0	0
T16	452012	11	0	0
T17	0	33	0	0
T18	0	18	0	0
T19	0	29	0	0
T20	0	22	0	0
T21	0	17	0	0
T22	0	31	0	0
T23	0	9	0	0
T24	0	49	0	0
T26	43058	0	0	0
T27	5082	0	0	0
T28	804922	0	0	0
T29	345631	0	0	0
T30	677548	0	0	0
T31	114353	0	0	0
T32	496053	0	0	0
T33	284040	0	0	0
T34	193708	0	0	0
T35	0	6	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1282	0	0
T16	452012	27	0	0
T17	0	15	0	0
T18	0	18	0	0
T19	0	32	0	0
T20	0	8	0	0
T21	0	14	0	0
T22	0	18	0	0
T23	0	7	0	0
T24	0	43	0	0
T26	43058	0	0	0
T27	5082	0	0	0
T28	804922	0	0	0
T29	345631	0	0	0
T30	677548	0	0	0
T31	114353	0	0	0
T32	496053	0	0	0
T33	284040	0	0	0
T34	193708	0	0	0
T35	0	3	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1104	0	0
T16	452012	16	0	0
T17	0	5	0	0
T18	0	32	0	0
T19	0	38	0	0
T20	0	20	0	0
T21	0	16	0	0
T22	0	40	0	0
T23	0	8	0	0
T24	0	52	0	0
T26	43058	0	0	0
T27	5082	0	0	0
T28	804922	0	0	0
T29	345631	0	0	0
T30	677548	0	0	0
T31	114353	0	0	0
T32	496053	0	0	0
T33	284040	0	0	0
T34	193708	0	0	0
T35	0	4	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1208	0	0
T16	452012	19	0	0
T17	0	9	0	0
T18	0	2	0	0
T19	0	29	0	0
T20	0	18	0	0
T21	0	23	0	0
T22	0	36	0	0
T23	0	1	0	0
T24	0	43	0	0
T26	43058	0	0	0
T27	5082	0	0	0
T28	804922	0	0	0
T29	345631	0	0	0
T30	677548	0	0	0
T31	114353	0	0	0
T32	496053	0	0	0
T33	284040	0	0	0
T34	193708	0	0	0
T35	0	11	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1021	0	0
T16	452012	11	0	0
T17	0	10	0	0
T18	0	11	0	0
T19	0	41	0	0
T20	0	10	0	0
T21	0	17	0	0
T22	0	31	0	0
T23	0	16	0	0
T24	0	38	0	0
T26	43058	0	0	0
T27	5082	0	0	0
T28	804922	0	0	0
T29	345631	0	0	0
T30	677548	0	0	0
T31	114353	0	0	0
T32	496053	0	0	0
T33	284040	0	0	0
T34	193708	0	0	0
T35	0	13	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1108	0	0
T16	452012	25	0	0
T17	0	7	0	0
T18	0	14	0	0
T19	0	29	0	0
T20	0	14	0	0
T21	0	30	0	0
T22	0	40	0	0
T23	0	4	0	0
T24	0	44	0	0
T26	43058	0	0	0
T27	5082	0	0	0
T28	804922	0	0	0
T29	345631	0	0	0
T30	677548	0	0	0
T31	114353	0	0	0
T32	496053	0	0	0
T33	284040	0	0	0
T34	193708	0	0	0
T35	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1452	0	0
T5	643476	9	0	0
T6	825202	0	0	0
T7	125423	0	0	0
T8	317611	0	0	0
T9	237664	0	0	0
T10	942973	0	0	0
T11	410574	0	0	0
T12	107659	0	0	0
T13	297117	0	0	0
T15	6452	0	0	0
T16	0	16	0	0
T17	0	28	0	0
T18	0	30	0	0
T19	0	25	0	0
T21	0	25	0	0
T22	0	40	0	0
T36	0	5	0	0
T37	0	11	0	0
T38	0	16	0	0