Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1205791	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1182331

1

T1

1464

T2

299

T3

926

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2106746	1			T1	2498		T3	1697		T4	1656
values[0x0]	140480	1			T1	154		T2	383		T3	105
values[0x1]	140896	1			T1	151		T2	390		T3	104

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	965697	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1422425

1

T1

1726

T2

365

T3

1143

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9596	1			T1	4		T2	5		T3	13
valid_sources[0x01]	9818	1			T1	6		T2	6		T3	12
valid_sources[0x02]	6821	1			T1	2		T2	2		T3	6
valid_sources[0x03]	11234	1			T1	30		T2	3		T3	6
valid_sources[0x04]	6851	1			T1	17		T2	5		T3	4
valid_sources[0x05]	11275	1			T1	8		T2	4		T3	8
valid_sources[0x06]	6924	1			T1	9		T2	2		T3	13
valid_sources[0x07]	13234	1			T1	11		T2	2		T3	13
valid_sources[0x08]	7355	1			T1	9		T2	1		T3	5
valid_sources[0x09]	10177	1			T1	9		T2	2		T3	6
valid_sources[0x0a]	6984	1			T1	7		T2	3		T3	1
valid_sources[0x0b]	10212	1			T1	13		T2	4		T3	7
valid_sources[0x0c]	7137	1			T1	14		T2	3		T3	4
valid_sources[0x0d]	7612	1			T1	32		T2	2		T3	9
valid_sources[0x0e]	14020	1			T1	6		T2	1		T3	6
valid_sources[0x0f]	11033	1			T1	5		T2	3		T3	7
valid_sources[0x10]	7165	1			T1	12		T2	6		T4	3
valid_sources[0x11]	9672	1			T1	14		T2	2		T3	16
valid_sources[0x12]	7958	1			T1	8		T2	3		T3	5
valid_sources[0x13]	12101	1			T1	43		T2	1		T3	10
valid_sources[0x14]	8394	1			T1	5		T2	2		T3	14
valid_sources[0x15]	6803	1			T1	9		T2	1		T3	10
valid_sources[0x16]	7225	1			T1	8		T2	4		T3	2
valid_sources[0x17]	12366	1			T1	5		T2	3		T3	9
valid_sources[0x18]	6978	1			T1	5		T2	2		T3	4
valid_sources[0x19]	11285	1			T1	9		T3	3		T4	6
valid_sources[0x1a]	7187	1			T1	4		T2	4		T3	4
valid_sources[0x1b]	16000	1			T1	6		T2	3		T3	4
valid_sources[0x1c]	16015	1			T1	15		T2	3		T3	11
valid_sources[0x1d]	9737	1			T1	6		T2	1		T3	10
valid_sources[0x1e]	8278	1			T1	9		T2	6		T3	7
valid_sources[0x1f]	8363	1			T1	10		T2	5		T3	15
valid_sources[0x20]	16327	1			T1	11		T2	5		T3	3
valid_sources[0x21]	11278	1			T1	8		T2	2		T3	4
valid_sources[0x22]	8447	1			T1	22		T2	10		T3	5
valid_sources[0x23]	11763	1			T1	7		T2	4		T3	2
valid_sources[0x24]	6896	1			T1	16		T2	1		T3	8
valid_sources[0x25]	11292	1			T1	13		T2	4		T3	6
valid_sources[0x26]	7273	1			T1	10		T2	2		T3	15
valid_sources[0x27]	11186	1			T1	3		T2	3		T3	9
valid_sources[0x28]	8191	1			T1	1		T2	4		T3	6
valid_sources[0x29]	8120	1			T1	17		T2	8		T3	4
valid_sources[0x2a]	19904	1			T1	4		T2	5		T3	13
valid_sources[0x2b]	11507	1			T1	11		T2	4		T3	7
valid_sources[0x2c]	8887	1			T1	4		T2	6		T3	13
valid_sources[0x2d]	7288	1			T1	9		T2	5		T3	5
valid_sources[0x2e]	8300	1			T1	14		T2	1		T3	8
valid_sources[0x2f]	7472	1			T1	9		T2	2		T3	11
valid_sources[0x30]	7264	1			T1	6		T2	3		T3	9
valid_sources[0x31]	7012	1			T1	9		T2	4		T3	7
valid_sources[0x32]	8267	1			T1	7		T3	6		T4	4
valid_sources[0x33]	7173	1			T1	32		T2	3		T3	1
valid_sources[0x34]	8781	1			T1	5		T2	5		T3	11
valid_sources[0x35]	7306	1			T1	17		T2	2		T3	5
valid_sources[0x36]	7073	1			T1	4		T2	4		T3	3
valid_sources[0x37]	7322	1			T1	12		T2	3		T3	14
valid_sources[0x38]	7017	1			T1	2		T2	5		T3	3
valid_sources[0x39]	10362	1			T1	36		T2	4		T3	6
valid_sources[0x3a]	24623	1			T1	60		T2	2		T3	2
valid_sources[0x3b]	7096	1			T1	19		T2	6		T3	14
valid_sources[0x3c]	9640	1			T1	6		T2	2		T3	13
valid_sources[0x3d]	8309	1			T1	10		T2	3		T3	2
valid_sources[0x3e]	8023	1			T1	12		T2	3		T3	6
valid_sources[0x3f]	8843	1			T1	8		T2	1		T3	4
valid_sources[0x40]	7414	1			T1	40		T2	4		T3	9
valid_sources[0x41]	7074	1			T1	7		T2	5		T3	4
valid_sources[0x42]	8121	1			T1	9		T3	8		T4	6
valid_sources[0x43]	15676	1			T1	7		T3	6		T4	11
valid_sources[0x44]	18655	1			T1	4		T2	5		T3	10
valid_sources[0x45]	15637	1			T1	12		T2	3		T3	10
valid_sources[0x46]	7122	1			T1	9		T2	3		T3	4
valid_sources[0x47]	8053	1			T1	4		T2	5		T3	5
valid_sources[0x48]	17640	1			T1	11		T2	1		T3	7
valid_sources[0x49]	7257	1			T1	7		T3	5		T4	6
valid_sources[0x4a]	7445	1			T1	9		T2	3		T3	13
valid_sources[0x4b]	7093	1			T1	11		T2	1		T3	6
valid_sources[0x4c]	11942	1			T1	6		T2	5		T3	7
valid_sources[0x4d]	9045	1			T1	10		T2	6		T3	4
valid_sources[0x4e]	13715	1			T1	13		T2	5		T3	5
valid_sources[0x4f]	6960	1			T1	43		T2	4		T3	5
valid_sources[0x50]	7118	1			T1	3		T2	2		T3	10
valid_sources[0x51]	8171	1			T1	8		T2	1		T3	6
valid_sources[0x52]	7072	1			T1	18		T2	5		T3	7
valid_sources[0x53]	8075	1			T1	6		T2	2		T3	4
valid_sources[0x54]	9927	1			T1	5		T2	5		T3	7
valid_sources[0x55]	11919	1			T1	8		T2	5		T3	2
valid_sources[0x56]	8106	1			T1	11		T3	5		T4	6
valid_sources[0x57]	6976	1			T1	26		T2	2		T3	7
valid_sources[0x58]	7827	1			T1	46		T2	5		T3	14
valid_sources[0x59]	7048	1			T1	8		T2	7		T3	4
valid_sources[0x5a]	6969	1			T1	1		T2	6		T3	16
valid_sources[0x5b]	7193	1			T1	7		T2	4		T3	8
valid_sources[0x5c]	7466	1			T1	35		T2	6		T3	8
valid_sources[0x5d]	7147	1			T1	22		T2	2		T3	6
valid_sources[0x5e]	7291	1			T1	20		T2	1		T3	6
valid_sources[0x5f]	7450	1			T1	10		T2	5		T3	9
valid_sources[0x60]	7228	1			T1	5		T2	4		T3	2
valid_sources[0x61]	7527	1			T1	3		T2	2		T3	10
valid_sources[0x62]	6850	1			T1	3		T3	6		T4	15
valid_sources[0x63]	7209	1			T1	6		T2	5		T3	4
valid_sources[0x64]	8049	1			T1	2		T2	2		T3	2
valid_sources[0x65]	7598	1			T1	18		T2	3		T3	16
valid_sources[0x66]	7526	1			T1	8		T2	7		T3	9
valid_sources[0x67]	11354	1			T1	3		T2	5		T3	5
valid_sources[0x68]	9941	1			T1	10		T2	2		T3	7
valid_sources[0x69]	9682	1			T1	5		T2	2		T3	14
valid_sources[0x6a]	10005	1			T1	2		T2	6		T3	5
valid_sources[0x6b]	7116	1			T1	4		T2	3		T3	8
valid_sources[0x6c]	7036	1			T1	6		T2	5		T3	9
valid_sources[0x6d]	7541	1			T1	5		T2	3		T3	8
valid_sources[0x6e]	7528	1			T1	4		T2	5		T3	10
valid_sources[0x6f]	10698	1			T1	13		T2	1		T3	8
valid_sources[0x70]	7922	1			T1	7		T2	3		T3	3
valid_sources[0x71]	8224	1			T1	12		T2	3		T3	5
valid_sources[0x72]	7055	1			T1	6		T2	4		T3	16
valid_sources[0x73]	7278	1			T1	7		T2	3		T3	4
valid_sources[0x74]	9461	1			T1	5		T2	6		T3	11
valid_sources[0x75]	13965	1			T1	11		T2	3		T3	18
valid_sources[0x76]	13012	1			T1	10		T2	3		T3	14
valid_sources[0x77]	8655	1			T1	12		T2	8		T3	4
valid_sources[0x78]	6959	1			T1	5		T2	2		T3	6
valid_sources[0x79]	8100	1			T1	3		T2	2		T3	3
valid_sources[0x7a]	6945	1			T1	6		T2	2		T3	11
valid_sources[0x7b]	7265	1			T1	16		T3	7		T4	10
valid_sources[0x7c]	7246	1			T1	14		T2	2		T3	4
valid_sources[0x7d]	6844	1			T1	21		T2	6		T3	11
valid_sources[0x7e]	10845	1			T1	3		T2	2		T3	7
valid_sources[0x7f]	8161	1			T1	7		T2	8		T3	9
valid_sources[0x80]	17838	1			T1	2		T2	6		T3	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1050145

1

T1

1303

T3

821

T4

817

values[0x0]

all_enables

biggest_size

77051

1

T1

95

T2

163

T3

65

values[0x1]

all_enables

biggest_size

55135

1

T1

66

T2

136

T3

40