Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	26469	1			T1	22		T2	203		T3	16
auto[PWRUP]	125	1			T2	1		T66	3		T68	1
auto[ONEST_0]	62	1			T66	3		T68	1		T44	1
auto[ONEST_021]	17	1			T68	2		T67	1		T202	1
auto[ONEST_1]	72	1			T2	4		T66	2		T68	1
auto[ONEST_DONE]	3	1			T69	1		T70	1		T203	1
auto[LP_0]	88	1			T2	2		T66	2		T68	1
auto[LP_021]	26	1			T67	1		T27	2		T204	2
auto[LP_1]	124	1			T2	1		T66	2		T68	3
auto[LP_EVAL]	61	1			T43	1		T66	1		T44	2
auto[LP_SLP]	460	1			T2	4		T66	5		T68	9
auto[LP_PWRUP]	23	1			T68	2		T27	1		T70	1
auto[NP_0]	133	1			T2	4		T66	1		T68	3
auto[NP_021]	37	1			T68	2		T67	1		T202	1
auto[NP_1]	125	1			T66	3		T68	2		T67	3
auto[NP_EVAL]	34	1			T2	1		T68	1		T67	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

4

1

T205

1

T206

1

T207

1

min

25989

1

T1

22

T2

200

T3

16

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	25994	1			T1	22		T2	200		T3	16
pow[0x1]	6	1			T27	1		T208	1		T209	1
pow[0x2]	16	1			T66	1		T27	1		T210	1
pow[0x3]	37	1			T66	2		T211	2		T70	4
pow[0x4]	57	1			T2	1		T66	1		T68	2
pow[0x5]	145	1			T2	2		T43	1		T66	3
pow[0x6]	222	1			T2	1		T43	1		T66	4
pow[0x7]	459	1			T2	6		T66	5		T68	9

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

166

1

T2

4

T66

1

T68

3

min

25566

1

T1

22

T2

193

T3

16

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	25566	1			T1	22		T2	193		T3	16
pow[0x4]	1	1			T212	1		-	-		-	-
pow[0x6]	1	1			T213	1		-	-		-	-
pow[0x7]	1	1			T214	1		-	-		-	-
pow[0x8]	3	1			T215	1		T216	1		T217	1
pow[0x9]	8	1			T209	1		T218	1		T219	1
pow[0xa]	12	1			T27	1		T202	1		T220	1
pow[0xb]	35	1			T2	1		T66	1		T67	1
pow[0xc]	54	1			T2	2		T66	1		T68	3
pow[0xd]	143	1			T2	2		T43	1		T66	2
pow[0xe]	249	1			T2	1		T66	1		T68	1
pow[0xf]	518	1			T2	7		T43	1		T66	11