Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.33	93.33	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	93.33	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.33	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	3	42	93.33

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	2	14	87.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2083	1			T2	7		T7	5		T60	3
auto[PWRUP]	118	1			T2	2		T66	2		T68	4
auto[ONEST_0]	58	1			T2	1		T66	1		T68	1
auto[ONEST_021]	18	1			T66	1		T45	1		T27	1
auto[ONEST_1]	78	1			T2	1		T40	1		T66	1
auto[ONEST_DONE]	6	1			T66	2		T214	1		T346	1
auto[LP_0]	103	1			T2	1		T66	2		T68	3
auto[LP_021]	22	1			T66	2		T27	1		T48	1
auto[LP_1]	108	1			T68	3		T44	1		T45	1
auto[LP_EVAL]	45	1			T43	1		T66	1		T68	2
auto[LP_SLP]	459	1			T2	8		T40	1		T66	7
auto[LP_PWRUP]	20	1			T43	1		T68	1		T347	1
auto[NP_0]	172	1			T2	3		T43	1		T40	1
auto[NP_021]	29	1			T43	1		T45	1		T69	1
auto[NP_1]	191	1			T2	1		T66	4		T68	2
auto[NP_EVAL]	22	1			T2	1		T68	2		T49	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T27

2

T70

1

T348

1

min

1721

1

T2

8

T7

5

T60

3

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1737	1			T2	8		T7	5		T60	3
pow[0x1]	8	1			T45	1		T202	1		T204	1
pow[0x2]	16	1			T27	1		T211	1		T349	1
pow[0x3]	31	1			T2	1		T68	1		T27	1
pow[0x4]	58	1			T2	1		T68	1		T67	2
pow[0x5]	119	1			T2	2		T43	1		T66	2
pow[0x6]	211	1			T2	3		T66	4		T68	4
pow[0x7]	479	1			T2	4		T43	1		T66	6

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

156

1

T2

2

T66

3

T68

2

min

1280

1

T2

4

T7

5

T60

3

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	2	14	87.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1289	1			T2	4		T7	5		T60	3
pow[0x1]	15	1			T45	4		T50	2		T13	1
pow[0x2]	13	1			T12	1		T13	1		T15	2
pow[0x3]	24	1			T43	2		T47	1		T49	4
pow[0x4]	11	1			T44	3		T12	1		T210	1
pow[0x7]	5	1			T69	1		T206	1		T204	1
pow[0x8]	4	1			T212	1		T350	1		T351	1
pow[0x9]	11	1			T68	1		T348	1		T212	1
pow[0xa]	12	1			T2	1		T66	2		T211	1
pow[0xb]	33	1			T68	1		T27	1		T69	1
pow[0xc]	50	1			T2	1		T66	1		T67	1
pow[0xd]	120	1			T66	1		T68	3		T27	5
pow[0xe]	263	1			T2	3		T66	5		T68	8
pow[0xf]	499	1			T2	9		T43	1		T66	7