Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2084	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2238	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2220	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2226	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2285	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2101	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2415	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2225	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2280	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2258	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2296	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2287	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2354	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2461	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2234	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2256	0	0
adc_en_ctl_rd_A	2147483647	1718	0	0
adc_fsm_rst_rd_A	2147483647	1639	0	0
adc_intr_ctl_rd_A	2147483647	2613	0	0
adc_lp_sample_ctl_rd_A	2147483647	1504	0	0
adc_pd_ctl_rd_A	2147483647	1935	0	0
adc_sample_ctl_rd_A	2147483647	1648	0	0
adc_wakeup_ctl_rd_A	2147483647	1842	0	0
intr_enable_rd_A	2147483647	2311	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2084	0	0
T12	167269	5	0	0
T13	0	36	0	0
T14	0	23	0	0
T15	0	30	0	0
T16	0	23	0	0
T17	0	45	0	0
T18	0	40	0	0
T19	0	25	0	0
T20	0	35	0	0
T21	0	30	0	0
T22	156530	0	0	0
T23	660970	0	0	0
T24	362262	0	0	0
T25	494880	0	0	0
T26	827619	0	0	0
T27	173432	0	0	0
T28	589772	0	0	0
T29	411221	0	0	0
T30	956937	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2238	0	0
T12	167269	12	0	0
T13	0	28	0	0
T14	0	9	0	0
T15	0	38	0	0
T16	0	16	0	0
T17	0	37	0	0
T18	0	41	0	0
T19	0	33	0	0
T20	0	46	0	0
T21	0	13	0	0
T22	156530	0	0	0
T23	660970	0	0	0
T24	362262	0	0	0
T25	494880	0	0	0
T26	827619	0	0	0
T27	173432	0	0	0
T28	589772	0	0	0
T29	411221	0	0	0
T30	956937	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2220	0	0
T12	167269	7	0	0
T13	0	47	0	0
T14	0	12	0	0
T15	0	46	0	0
T16	0	15	0	0
T17	0	48	0	0
T18	0	32	0	0
T19	0	16	0	0
T20	0	24	0	0
T21	0	5	0	0
T22	156530	0	0	0
T23	660970	0	0	0
T24	362262	0	0	0
T25	494880	0	0	0
T26	827619	0	0	0
T27	173432	0	0	0
T28	589772	0	0	0
T29	411221	0	0	0
T30	956937	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2226	0	0
T12	167269	12	0	0
T13	0	38	0	0
T14	0	24	0	0
T15	0	50	0	0
T16	0	8	0	0
T17	0	37	0	0
T18	0	44	0	0
T19	0	17	0	0
T20	0	25	0	0
T21	0	21	0	0
T22	156530	0	0	0
T23	660970	0	0	0
T24	362262	0	0	0
T25	494880	0	0	0
T26	827619	0	0	0
T27	173432	0	0	0
T28	589772	0	0	0
T29	411221	0	0	0
T30	956937	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2285	0	0
T12	167269	19	0	0
T13	0	21	0	0
T14	0	18	0	0
T15	0	52	0	0
T16	0	12	0	0
T17	0	31	0	0
T18	0	42	0	0
T19	0	10	0	0
T20	0	36	0	0
T21	0	4	0	0
T22	156530	0	0	0
T23	660970	0	0	0
T24	362262	0	0	0
T25	494880	0	0	0
T26	827619	0	0	0
T27	173432	0	0	0
T28	589772	0	0	0
T29	411221	0	0	0
T30	956937	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2101	0	0
T12	167269	23	0	0
T13	0	27	0	0
T14	0	12	0	0
T15	0	37	0	0
T16	0	20	0	0
T17	0	39	0	0
T18	0	28	0	0
T19	0	10	0	0
T20	0	32	0	0
T21	0	12	0	0
T22	156530	0	0	0
T23	660970	0	0	0
T24	362262	0	0	0
T25	494880	0	0	0
T26	827619	0	0	0
T27	173432	0	0	0
T28	589772	0	0	0
T29	411221	0	0	0
T30	956937	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2415	0	0
T12	167269	25	0	0
T13	0	47	0	0
T14	0	18	0	0
T15	0	43	0	0
T16	0	23	0	0
T17	0	33	0	0
T18	0	45	0	0
T19	0	13	0	0
T20	0	30	0	0
T21	0	14	0	0
T22	156530	0	0	0
T23	660970	0	0	0
T24	362262	0	0	0
T25	494880	0	0	0
T26	827619	0	0	0
T27	173432	0	0	0
T28	589772	0	0	0
T29	411221	0	0	0
T30	956937	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2225	0	0
T12	167269	24	0	0
T13	0	43	0	0
T14	0	17	0	0
T15	0	24	0	0
T16	0	20	0	0
T17	0	43	0	0
T18	0	28	0	0
T19	0	10	0	0
T20	0	30	0	0
T21	0	5	0	0
T22	156530	0	0	0
T23	660970	0	0	0
T24	362262	0	0	0
T25	494880	0	0	0
T26	827619	0	0	0
T27	173432	0	0	0
T28	589772	0	0	0
T29	411221	0	0	0
T30	956937	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2280	0	0
T12	167269	20	0	0
T13	0	42	0	0
T14	0	15	0	0
T15	0	31	0	0
T16	0	25	0	0
T17	0	50	0	0
T18	0	50	0	0
T19	0	15	0	0
T20	0	46	0	0
T21	0	14	0	0
T22	156530	0	0	0
T23	660970	0	0	0
T24	362262	0	0	0
T25	494880	0	0	0
T26	827619	0	0	0
T27	173432	0	0	0
T28	589772	0	0	0
T29	411221	0	0	0
T30	956937	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2258	0	0
T12	167269	13	0	0
T13	0	43	0	0
T14	0	18	0	0
T15	0	20	0	0
T16	0	20	0	0
T17	0	48	0	0
T18	0	48	0	0
T19	0	17	0	0
T20	0	34	0	0
T21	0	20	0	0
T22	156530	0	0	0
T23	660970	0	0	0
T24	362262	0	0	0
T25	494880	0	0	0
T26	827619	0	0	0
T27	173432	0	0	0
T28	589772	0	0	0
T29	411221	0	0	0
T30	956937	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2296	0	0
T12	167269	24	0	0
T13	0	35	0	0
T14	0	18	0	0
T15	0	32	0	0
T16	0	20	0	0
T17	0	45	0	0
T18	0	37	0	0
T19	0	25	0	0
T20	0	30	0	0
T21	0	17	0	0
T22	156530	0	0	0
T23	660970	0	0	0
T24	362262	0	0	0
T25	494880	0	0	0
T26	827619	0	0	0
T27	173432	0	0	0
T28	589772	0	0	0
T29	411221	0	0	0
T30	956937	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2287	0	0
T12	167269	20	0	0
T13	0	28	0	0
T14	0	23	0	0
T15	0	49	0	0
T16	0	17	0	0
T17	0	52	0	0
T18	0	45	0	0
T19	0	18	0	0
T20	0	37	0	0
T21	0	9	0	0
T22	156530	0	0	0
T23	660970	0	0	0
T24	362262	0	0	0
T25	494880	0	0	0
T26	827619	0	0	0
T27	173432	0	0	0
T28	589772	0	0	0
T29	411221	0	0	0
T30	956937	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2354	0	0
T12	167269	16	0	0
T13	0	35	0	0
T14	0	19	0	0
T15	0	37	0	0
T16	0	27	0	0
T17	0	33	0	0
T18	0	37	0	0
T19	0	19	0	0
T20	0	44	0	0
T21	0	11	0	0
T22	156530	0	0	0
T23	660970	0	0	0
T24	362262	0	0	0
T25	494880	0	0	0
T26	827619	0	0	0
T27	173432	0	0	0
T28	589772	0	0	0
T29	411221	0	0	0
T30	956937	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2461	0	0
T12	167269	19	0	0
T13	0	37	0	0
T14	0	24	0	0
T15	0	35	0	0
T16	0	16	0	0
T17	0	30	0	0
T18	0	46	0	0
T19	0	12	0	0
T20	0	25	0	0
T21	0	18	0	0
T22	156530	0	0	0
T23	660970	0	0	0
T24	362262	0	0	0
T25	494880	0	0	0
T26	827619	0	0	0
T27	173432	0	0	0
T28	589772	0	0	0
T29	411221	0	0	0
T30	956937	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2234	0	0
T12	167269	20	0	0
T13	0	38	0	0
T14	0	26	0	0
T15	0	48	0	0
T16	0	20	0	0
T17	0	39	0	0
T18	0	33	0	0
T19	0	19	0	0
T20	0	36	0	0
T21	0	2	0	0
T22	156530	0	0	0
T23	660970	0	0	0
T24	362262	0	0	0
T25	494880	0	0	0
T26	827619	0	0	0
T27	173432	0	0	0
T28	589772	0	0	0
T29	411221	0	0	0
T30	956937	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2256	0	0
T12	167269	14	0	0
T13	0	31	0	0
T14	0	12	0	0
T15	0	51	0	0
T16	0	26	0	0
T17	0	28	0	0
T18	0	50	0	0
T19	0	20	0	0
T20	0	30	0	0
T21	0	4	0	0
T22	156530	0	0	0
T23	660970	0	0	0
T24	362262	0	0	0
T25	494880	0	0	0
T26	827619	0	0	0
T27	173432	0	0	0
T28	589772	0	0	0
T29	411221	0	0	0
T30	956937	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1718	0	0
T12	167269	18	0	0
T13	0	26	0	0
T14	0	5	0	0
T15	0	25	0	0
T16	0	15	0	0
T17	0	17	0	0
T18	0	30	0	0
T19	0	20	0	0
T20	0	29	0	0
T21	0	4	0	0
T22	156530	0	0	0
T23	660970	0	0	0
T24	362262	0	0	0
T25	494880	0	0	0
T26	827619	0	0	0
T27	173432	0	0	0
T28	589772	0	0	0
T29	411221	0	0	0
T30	956937	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1639	0	0
T12	167269	25	0	0
T13	0	48	0	0
T14	0	22	0	0
T15	0	54	0	0
T16	0	25	0	0
T17	0	58	0	0
T18	0	26	0	0
T19	0	14	0	0
T20	0	24	0	0
T21	0	9	0	0
T22	156530	0	0	0
T23	660970	0	0	0
T24	362262	0	0	0
T25	494880	0	0	0
T26	827619	0	0	0
T27	173432	0	0	0
T28	589772	0	0	0
T29	411221	0	0	0
T30	956937	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2613	0	0
T12	167269	27	0	0
T13	0	37	0	0
T14	0	11	0	0
T15	0	49	0	0
T16	0	11	0	0
T17	0	52	0	0
T18	0	52	0	0
T19	0	16	0	0
T20	0	37	0	0
T21	0	3	0	0
T22	156530	0	0	0
T23	660970	0	0	0
T24	362262	0	0	0
T25	494880	0	0	0
T26	827619	0	0	0
T27	173432	0	0	0
T28	589772	0	0	0
T29	411221	0	0	0
T30	956937	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1504	0	0
T12	167269	9	0	0
T13	0	21	0	0
T14	0	25	0	0
T15	0	31	0	0
T16	0	18	0	0
T17	0	34	0	0
T18	0	40	0	0
T19	0	12	0	0
T20	0	51	0	0
T21	0	7	0	0
T22	156530	0	0	0
T23	660970	0	0	0
T24	362262	0	0	0
T25	494880	0	0	0
T26	827619	0	0	0
T27	173432	0	0	0
T28	589772	0	0	0
T29	411221	0	0	0
T30	956937	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1935	0	0
T12	167269	10	0	0
T13	0	37	0	0
T14	0	18	0	0
T15	0	32	0	0
T16	0	20	0	0
T17	0	29	0	0
T18	0	35	0	0
T19	0	23	0	0
T20	0	22	0	0
T21	0	15	0	0
T22	156530	0	0	0
T23	660970	0	0	0
T24	362262	0	0	0
T25	494880	0	0	0
T26	827619	0	0	0
T27	173432	0	0	0
T28	589772	0	0	0
T29	411221	0	0	0
T30	956937	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1648	0	0
T12	167269	6	0	0
T13	0	30	0	0
T14	0	11	0	0
T15	0	35	0	0
T16	0	12	0	0
T17	0	35	0	0
T18	0	56	0	0
T19	0	18	0	0
T20	0	42	0	0
T21	0	16	0	0
T22	156530	0	0	0
T23	660970	0	0	0
T24	362262	0	0	0
T25	494880	0	0	0
T26	827619	0	0	0
T27	173432	0	0	0
T28	589772	0	0	0
T29	411221	0	0	0
T30	956937	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1842	0	0
T12	167269	18	0	0
T13	0	56	0	0
T14	0	15	0	0
T15	0	46	0	0
T16	0	7	0	0
T17	0	37	0	0
T18	0	42	0	0
T19	0	18	0	0
T20	0	50	0	0
T21	0	6	0	0
T22	156530	0	0	0
T23	660970	0	0	0
T24	362262	0	0	0
T25	494880	0	0	0
T26	827619	0	0	0
T27	173432	0	0	0
T28	589772	0	0	0
T29	411221	0	0	0
T30	956937	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2311	0	0
T12	0	20	0	0
T13	0	41	0	0
T14	0	38	0	0
T15	0	40	0	0
T16	0	16	0	0
T17	0	36	0	0
T18	0	32	0	0
T31	742617	1	0	0
T32	0	13	0	0
T33	0	30	0	0
T34	155771	0	0	0
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