Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1151146	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1128379

1

T4

7

T1

1431

T2

150

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2006043	1			T4	1		T1	2535		T2	170
values[0x0]	136456	1			T4	12		T1	141		T2	33
values[0x1]	137026	1			T4	8		T1	141		T2	32

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	922465	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1357060

1

T4

11

T1

1717

T2

166

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6106	1			T2	1		T3	28		T5	8
valid_sources[0x01]	10849	1			T2	1		T3	43		T5	5
valid_sources[0x02]	11331	1			T2	1		T3	26		T5	9
valid_sources[0x03]	6647	1			T2	1		T3	26		T5	25
valid_sources[0x04]	10861	1			T2	1		T3	29		T5	20
valid_sources[0x05]	9064	1			T2	1		T3	33		T5	22
valid_sources[0x06]	7105	1			T3	30		T5	1		T8	23
valid_sources[0x07]	7895	1			T3	34		T5	27		T8	23
valid_sources[0x08]	6490	1			T2	1		T3	41		T5	13
valid_sources[0x09]	7076	1			T2	2		T3	42		T5	14
valid_sources[0x0a]	6686	1			T2	1		T3	42		T5	19
valid_sources[0x0b]	8461	1			T3	47		T5	1		T8	11
valid_sources[0x0c]	8665	1			T2	1		T3	22		T5	19
valid_sources[0x0d]	7832	1			T2	1		T3	16		T5	5
valid_sources[0x0e]	9435	1			T3	41		T5	10		T7	10
valid_sources[0x0f]	11191	1			T2	1		T3	34		T5	9
valid_sources[0x10]	7074	1			T2	1		T3	23		T5	9
valid_sources[0x11]	6716	1			T3	25		T5	14		T8	26
valid_sources[0x12]	6320	1			T3	33		T8	18		T9	2
valid_sources[0x13]	10934	1			T3	46		T5	16		T8	19
valid_sources[0x14]	13759	1			T3	37		T5	7		T8	21
valid_sources[0x15]	13515	1			T1	2817		T3	40		T5	23
valid_sources[0x16]	6525	1			T2	1		T3	14		T5	6
valid_sources[0x17]	8882	1			T3	26		T5	20		T8	23
valid_sources[0x18]	6604	1			T2	1		T3	33		T5	29
valid_sources[0x19]	6550	1			T3	40		T5	11		T8	15
valid_sources[0x1a]	6583	1			T2	2		T3	61		T5	5
valid_sources[0x1b]	6592	1			T2	2		T3	27		T5	9
valid_sources[0x1c]	6659	1			T2	1		T3	29		T5	13
valid_sources[0x1d]	7949	1			T2	2		T3	32		T5	39
valid_sources[0x1e]	19678	1			T2	1		T3	26		T5	22
valid_sources[0x1f]	11646	1			T2	1		T3	32		T5	9
valid_sources[0x20]	7506	1			T2	1		T3	13		T5	32
valid_sources[0x21]	6756	1			T2	1		T3	30		T5	11
valid_sources[0x22]	7758	1			T2	1		T3	33		T5	7
valid_sources[0x23]	6200	1			T3	29		T5	12		T8	16
valid_sources[0x24]	6422	1			T4	3		T2	2		T3	58
valid_sources[0x25]	21392	1			T3	30		T5	14		T8	25
valid_sources[0x26]	6309	1			T2	1		T3	29		T5	24
valid_sources[0x27]	6518	1			T3	44		T5	38		T8	21
valid_sources[0x28]	7772	1			T3	28		T5	19		T8	19
valid_sources[0x29]	6511	1			T2	1		T3	33		T5	7
valid_sources[0x2a]	7651	1			T3	29		T5	19		T8	21
valid_sources[0x2b]	7462	1			T3	39		T5	21		T8	17
valid_sources[0x2c]	13893	1			T2	1		T3	36		T7	4
valid_sources[0x2d]	6517	1			T2	1		T3	24		T5	9
valid_sources[0x2e]	6470	1			T2	1		T3	33		T5	5
valid_sources[0x2f]	10396	1			T2	1		T3	31		T5	2
valid_sources[0x30]	6359	1			T2	1		T3	28		T5	32
valid_sources[0x31]	8092	1			T2	1		T3	24		T5	26
valid_sources[0x32]	15421	1			T3	30		T5	10		T8	12
valid_sources[0x33]	7754	1			T3	37		T5	20		T8	9
valid_sources[0x34]	8175	1			T2	2		T3	24		T5	11
valid_sources[0x35]	9659	1			T3	48		T5	25		T8	11
valid_sources[0x36]	6710	1			T2	1		T3	28		T5	23
valid_sources[0x37]	8756	1			T2	1		T3	38		T5	19
valid_sources[0x38]	6298	1			T2	2		T3	20		T5	1
valid_sources[0x39]	6907	1			T3	42		T5	36		T8	15
valid_sources[0x3a]	7072	1			T2	1		T3	23		T5	10
valid_sources[0x3b]	6957	1			T2	1		T3	23		T5	53
valid_sources[0x3c]	6701	1			T3	47		T5	9		T8	13
valid_sources[0x3d]	6667	1			T2	1		T3	47		T5	18
valid_sources[0x3e]	6812	1			T3	48		T5	4		T7	22
valid_sources[0x3f]	6504	1			T2	2		T3	30		T5	43
valid_sources[0x40]	6469	1			T2	1		T3	38		T5	22
valid_sources[0x41]	9689	1			T2	1		T3	39		T5	16
valid_sources[0x42]	16218	1			T2	1		T3	31		T5	19
valid_sources[0x43]	16164	1			T3	45		T5	13		T8	15
valid_sources[0x44]	11894	1			T2	1		T3	31		T5	20
valid_sources[0x45]	6893	1			T3	41		T5	8		T8	20
valid_sources[0x46]	6983	1			T2	1		T3	27		T5	10
valid_sources[0x47]	7205	1			T2	2		T3	35		T5	22
valid_sources[0x48]	10744	1			T3	24		T5	16		T8	16
valid_sources[0x49]	15614	1			T2	1		T3	30		T5	14
valid_sources[0x4a]	6794	1			T3	42		T5	17		T7	12
valid_sources[0x4b]	6560	1			T2	4		T3	39		T5	7
valid_sources[0x4c]	7544	1			T2	1		T3	40		T5	9
valid_sources[0x4d]	6240	1			T2	1		T3	43		T5	12
valid_sources[0x4e]	11279	1			T3	42		T5	41		T8	18
valid_sources[0x4f]	7013	1			T2	1		T3	34		T5	12
valid_sources[0x50]	16871	1			T3	29		T5	14		T8	22
valid_sources[0x51]	6421	1			T2	3		T3	21		T5	24
valid_sources[0x52]	10765	1			T2	1		T3	19		T5	33
valid_sources[0x53]	23868	1			T3	18		T5	14		T8	14
valid_sources[0x54]	6645	1			T2	1		T3	19		T5	24
valid_sources[0x55]	13812	1			T3	41		T5	24		T8	8
valid_sources[0x56]	9469	1			T2	1		T3	22		T5	34
valid_sources[0x57]	10308	1			T3	31		T5	12		T8	19
valid_sources[0x58]	6447	1			T3	17		T5	10		T8	12
valid_sources[0x59]	7383	1			T3	31		T5	37		T8	17
valid_sources[0x5a]	6943	1			T3	33		T5	4		T7	4
valid_sources[0x5b]	6581	1			T2	2		T3	31		T5	6
valid_sources[0x5c]	6415	1			T2	2		T3	26		T5	1
valid_sources[0x5d]	14107	1			T2	1		T3	18		T5	10
valid_sources[0x5e]	11835	1			T2	1		T3	40		T5	31
valid_sources[0x5f]	6582	1			T2	1		T3	31		T5	33
valid_sources[0x60]	10584	1			T3	29		T5	16		T8	16
valid_sources[0x61]	6780	1			T3	57		T5	26		T7	5
valid_sources[0x62]	7480	1			T2	1		T3	63		T5	11
valid_sources[0x63]	6367	1			T2	3		T3	22		T5	3
valid_sources[0x64]	9486	1			T3	25		T5	22		T8	14
valid_sources[0x65]	6362	1			T2	3		T3	34		T5	18
valid_sources[0x66]	10782	1			T3	19		T5	14		T7	1
valid_sources[0x67]	6644	1			T3	18		T5	17		T8	19
valid_sources[0x68]	6650	1			T2	2		T3	40		T5	24
valid_sources[0x69]	9410	1			T2	1		T3	33		T5	3
valid_sources[0x6a]	6733	1			T3	32		T5	12		T8	16
valid_sources[0x6b]	10895	1			T2	1		T3	56		T5	15
valid_sources[0x6c]	10936	1			T2	1		T3	28		T5	15
valid_sources[0x6d]	7537	1			T2	1		T3	50		T5	17
valid_sources[0x6e]	6710	1			T3	53		T5	7		T8	13
valid_sources[0x6f]	6657	1			T2	1		T3	36		T5	9
valid_sources[0x70]	17268	1			T3	14		T5	10		T8	17
valid_sources[0x71]	6732	1			T3	46		T5	6		T8	10
valid_sources[0x72]	8359	1			T2	2		T3	41		T5	28
valid_sources[0x73]	6648	1			T3	29		T5	5		T8	15
valid_sources[0x74]	6715	1			T2	1		T3	34		T5	25
valid_sources[0x75]	6579	1			T2	2		T3	30		T5	27
valid_sources[0x76]	11524	1			T2	3		T3	43		T5	10
valid_sources[0x77]	6446	1			T2	1		T3	31		T5	30
valid_sources[0x78]	9421	1			T3	25		T5	23		T8	14
valid_sources[0x79]	12804	1			T2	2		T3	38		T5	3
valid_sources[0x7a]	6404	1			T3	41		T5	24		T7	32
valid_sources[0x7b]	11018	1			T2	1		T3	62		T5	7
valid_sources[0x7c]	6969	1			T2	1		T3	25		T5	12
valid_sources[0x7d]	6368	1			T2	1		T3	47		T5	4
valid_sources[0x7e]	6689	1			T3	50		T5	68		T8	8
valid_sources[0x7f]	16029	1			T4	11		T3	37		T5	9
valid_sources[0x80]	10172	1			T3	41		T5	6		T6	61

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1000125

1

T1

1291

T2

95

T3

4066

values[0x0]

all_enables

biggest_size

74552

1

T4

5

T1

85

T2

29

values[0x1]

all_enables

biggest_size

53702

1

T4

2

T1

55

T2

26