Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg
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Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
88.89 88.89 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
adc_ctrl_fsm_reset_cg_inst 88.89 1 100 1 64 64




Group Instance : adc_ctrl_fsm_reset_cg_inst
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
88.89 1 100 1 64 64




Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 45 5 40 88.89


Variables for Group Instance adc_ctrl_fsm_reset_cg_inst
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
fsm_state_cp 17 1 16 94.12 100 1 1 0
lp_sample_cnt_min_max_cp 2 0 2 100.00 100 1 1 0
lp_sample_cnt_pow_cp 8 0 8 100.00 100 1 1 0
np_sample_cnt_min_max_cp 2 0 2 100.00 100 1 1 0
np_sample_cnt_pow_cp 16 4 12 75.00 100 1 1 0


Summary for Variable fsm_state_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 17 1 16 94.12


Automatically Generated Bins for fsm_state_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[NP_DONE] 0 1 1


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[PWRDN] 26559 1 T1 20 T3 14 T5 11
auto[PWRUP] 91 1 T26 3 T40 3 T39 1
auto[ONEST_0] 53 1 T26 1 T40 2 T41 1
auto[ONEST_021] 14 1 T47 2 T49 1 T178 1
auto[ONEST_1] 82 1 T40 3 T39 2 T43 2
auto[ONEST_DONE] 3 1 T179 1 T180 1 T181 1
auto[LP_0] 99 1 T26 1 T40 3 T42 1
auto[LP_021] 41 1 T40 2 T42 1 T43 1
auto[LP_1] 101 1 T40 2 T39 1 T42 3
auto[LP_EVAL] 56 1 T40 3 T39 5 T43 2
auto[LP_SLP] 433 1 T26 9 T40 11 T39 9
auto[LP_PWRUP] 24 1 T43 1 T44 1 T45 1
auto[NP_0] 127 1 T26 2 T40 2 T39 3
auto[NP_021] 31 1 T26 1 T40 1 T182 2
auto[NP_1] 122 1 T26 2 T40 3 T39 3
auto[NP_EVAL] 25 1 T40 2 T41 1 T47 1



Summary for Variable lp_sample_cnt_min_max_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for lp_sample_cnt_min_max_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
max 2 1 T40 1 T183 1 - -
min 26082 1 T1 20 T3 14 T5 11



Summary for Variable lp_sample_cnt_pow_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for lp_sample_cnt_pow_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
pow[0x0] 26090 1 T1 20 T3 14 T5 11
pow[0x1] 6 1 T184 1 T185 1 T186 1
pow[0x2] 9 1 T39 1 T187 1 T188 1
pow[0x3] 45 1 T40 3 T42 1 T41 1
pow[0x4] 54 1 T26 1 T42 2 T41 2
pow[0x5] 93 1 T40 3 T39 4 T42 2
pow[0x6] 198 1 T26 4 T40 6 T39 7
pow[0x7] 441 1 T26 6 T40 14 T39 8



Summary for Variable np_sample_cnt_min_max_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for np_sample_cnt_min_max_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
max 171 1 T26 3 T40 6 T39 4
min 25667 1 T1 20 T3 14 T5 11



Summary for Variable np_sample_cnt_pow_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 16 4 12 75.00


User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins
NAME   COUNT   AT LEAST   NUMBER   STATUS   
pow[0x1] 0 1 1
pow[0x2] 0 1 1
pow[0x3] 0 1 1
pow[0x4] 0 1 1


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
pow[0x0] 25667 1 T1 20 T3 14 T5 11
pow[0x5] 1 1 T189 1 - - - -
pow[0x6] 2 1 T41 1 T190 1 - -
pow[0x7] 3 1 T42 1 T182 1 T191 1
pow[0x8] 2 1 T129 1 T192 1 - -
pow[0x9] 3 1 T193 1 T194 1 T180 1
pow[0xa] 9 1 T39 1 T44 1 T129 1
pow[0xb] 26 1 T43 1 T46 1 T129 2
pow[0xc] 59 1 T26 2 T40 2 T39 1
pow[0xd] 141 1 T26 1 T40 5 T39 1
pow[0xe] 258 1 T26 2 T40 10 T39 6
pow[0xf] 490 1 T26 6 T40 16 T39 9