Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2038	1			T2	5		T3	4		T7	13
auto[PWRUP]	121	1			T2	1		T26	1		T16	1
auto[ONEST_0]	72	1			T13	1		T26	1		T40	1
auto[ONEST_021]	13	1			T178	1		T289	1		T334	1
auto[ONEST_1]	82	1			T7	1		T26	2		T40	7
auto[ONEST_DONE]	3	1			T190	1		T192	1		T335	1
auto[LP_0]	119	1			T26	2		T40	2		T42	1
auto[LP_021]	23	1			T40	1		T39	1		T46	1
auto[LP_1]	124	1			T13	1		T26	1		T40	4
auto[LP_EVAL]	39	1			T26	1		T40	3		T39	1
auto[LP_SLP]	483	1			T25	2		T26	15		T40	8
auto[LP_PWRUP]	32	1			T43	1		T44	1		T45	2
auto[NP_0]	149	1			T2	1		T13	1		T25	1
auto[NP_021]	41	1			T2	1		T25	1		T26	1
auto[NP_1]	180	1			T7	1		T13	1		T25	3
auto[NP_EVAL]	26	1			T7	1		T40	4		T39	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T26

1

T185

1

T336

1

min

1714

1

T2

8

T3

4

T7

16

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1730	1			T2	8		T3	4		T7	16
pow[0x1]	5	1			T20	1		T185	1		T216	1
pow[0x2]	15	1			T46	1		T48	1		T337	1
pow[0x3]	26	1			T13	1		T26	2		T44	1
pow[0x4]	65	1			T26	1		T40	6		T42	1
pow[0x5]	113	1			T40	1		T39	2		T42	2
pow[0x6]	205	1			T26	3		T40	7		T39	1
pow[0x7]	486	1			T26	8		T40	13		T39	6

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

190

1

T26

3

T40

5

T39

1

min

1218

1

T2

7

T3

4

T7

15

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1222	1			T2	7		T3	4		T7	15
pow[0x1]	9	1			T2	1		T7	1		T13	1
pow[0x2]	14	1			T16	1		T32	1		T33	1
pow[0x3]	10	1			T13	1		T33	2		T18	1
pow[0x4]	17	1			T25	3		T177	1		T231	1
pow[0x5]	1	1			T129	1		-	-		-	-
pow[0x6]	1	1			T338	1		-	-		-	-
pow[0x7]	3	1			T339	1		T340	1		T341	1
pow[0x8]	3	1			T182	1		T188	1		T179	1
pow[0x9]	6	1			T40	1		T258	2		T342	1
pow[0xa]	17	1			T26	1		T41	1		T47	2
pow[0xb]	27	1			T47	1		T45	1		T193	1
pow[0xc]	65	1			T26	2		T40	1		T39	2
pow[0xd]	127	1			T26	1		T40	7		T46	1
pow[0xe]	256	1			T26	6		T40	9		T39	2
pow[0xf]	547	1			T26	14		T40	15		T39	4