Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2147	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1891	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2098	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2030	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2001	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2040	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1952	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2068	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2136	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2186	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2041	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2212	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2098	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2208	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1909	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2063	0	0
adc_en_ctl_rd_A	2147483647	1724	0	0
adc_fsm_rst_rd_A	2147483647	1662	0	0
adc_intr_ctl_rd_A	2147483647	2232	0	0
adc_lp_sample_ctl_rd_A	2147483647	1654	0	0
adc_pd_ctl_rd_A	2147483647	1918	0	0
adc_sample_ctl_rd_A	2147483647	1396	0	0
adc_wakeup_ctl_rd_A	2147483647	1698	0	0
intr_enable_rd_A	2147483647	2234	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147	0	0
T13	355942	22	0	0
T14	492772	0	0	0
T15	538671	0	0	0
T16	188881	48	0	0
T17	0	20	0	0
T18	0	23	0	0
T19	0	24	0	0
T20	0	13	0	0
T21	0	18	0	0
T22	0	54	0	0
T23	0	27	0	0
T24	0	13	0	0
T25	409729	0	0	0
T26	127079	0	0	0
T27	101423	0	0	0
T28	112064	0	0	0
T29	496289	0	0	0
T30	851415	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1891	0	0
T13	355942	19	0	0
T14	492772	0	0	0
T15	538671	0	0	0
T16	188881	34	0	0
T17	0	20	0	0
T18	0	26	0	0
T19	0	14	0	0
T20	0	14	0	0
T21	0	18	0	0
T22	0	41	0	0
T23	0	34	0	0
T24	0	25	0	0
T25	409729	0	0	0
T26	127079	0	0	0
T27	101423	0	0	0
T28	112064	0	0	0
T29	496289	0	0	0
T30	851415	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2098	0	0
T13	355942	31	0	0
T14	492772	0	0	0
T15	538671	0	0	0
T16	188881	35	0	0
T17	0	15	0	0
T18	0	26	0	0
T19	0	19	0	0
T20	0	22	0	0
T21	0	18	0	0
T22	0	48	0	0
T23	0	16	0	0
T24	0	13	0	0
T25	409729	0	0	0
T26	127079	0	0	0
T27	101423	0	0	0
T28	112064	0	0	0
T29	496289	0	0	0
T30	851415	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2030	0	0
T13	355942	32	0	0
T14	492772	0	0	0
T15	538671	0	0	0
T16	188881	28	0	0
T17	0	14	0	0
T18	0	31	0	0
T19	0	21	0	0
T20	0	11	0	0
T21	0	30	0	0
T22	0	28	0	0
T23	0	27	0	0
T24	0	23	0	0
T25	409729	0	0	0
T26	127079	0	0	0
T27	101423	0	0	0
T28	112064	0	0	0
T29	496289	0	0	0
T30	851415	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2001	0	0
T13	355942	30	0	0
T14	492772	0	0	0
T15	538671	0	0	0
T16	188881	47	0	0
T17	0	22	0	0
T18	0	23	0	0
T19	0	13	0	0
T20	0	28	0	0
T21	0	16	0	0
T22	0	41	0	0
T23	0	47	0	0
T24	0	31	0	0
T25	409729	0	0	0
T26	127079	0	0	0
T27	101423	0	0	0
T28	112064	0	0	0
T29	496289	0	0	0
T30	851415	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2040	0	0
T13	355942	30	0	0
T14	492772	0	0	0
T15	538671	0	0	0
T16	188881	31	0	0
T17	0	16	0	0
T18	0	26	0	0
T19	0	25	0	0
T20	0	25	0	0
T21	0	37	0	0
T22	0	17	0	0
T23	0	40	0	0
T24	0	13	0	0
T25	409729	0	0	0
T26	127079	0	0	0
T27	101423	0	0	0
T28	112064	0	0	0
T29	496289	0	0	0
T30	851415	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1952	0	0
T13	355942	41	0	0
T14	492772	0	0	0
T15	538671	0	0	0
T16	188881	36	0	0
T17	0	13	0	0
T18	0	25	0	0
T19	0	9	0	0
T20	0	14	0	0
T21	0	25	0	0
T22	0	35	0	0
T23	0	45	0	0
T24	0	14	0	0
T25	409729	0	0	0
T26	127079	0	0	0
T27	101423	0	0	0
T28	112064	0	0	0
T29	496289	0	0	0
T30	851415	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2068	0	0
T13	355942	25	0	0
T14	492772	0	0	0
T15	538671	0	0	0
T16	188881	38	0	0
T17	0	15	0	0
T18	0	13	0	0
T19	0	13	0	0
T20	0	20	0	0
T21	0	23	0	0
T22	0	24	0	0
T23	0	46	0	0
T24	0	24	0	0
T25	409729	0	0	0
T26	127079	0	0	0
T27	101423	0	0	0
T28	112064	0	0	0
T29	496289	0	0	0
T30	851415	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2136	0	0
T13	355942	30	0	0
T14	492772	0	0	0
T15	538671	0	0	0
T16	188881	29	0	0
T17	0	7	0	0
T18	0	23	0	0
T19	0	18	0	0
T20	0	16	0	0
T21	0	19	0	0
T22	0	47	0	0
T23	0	20	0	0
T24	0	14	0	0
T25	409729	0	0	0
T26	127079	0	0	0
T27	101423	0	0	0
T28	112064	0	0	0
T29	496289	0	0	0
T30	851415	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2186	0	0
T13	355942	13	0	0
T14	492772	0	0	0
T15	538671	0	0	0
T16	188881	39	0	0
T17	0	7	0	0
T18	0	14	0	0
T19	0	25	0	0
T20	0	9	0	0
T21	0	15	0	0
T22	0	31	0	0
T23	0	23	0	0
T24	0	22	0	0
T25	409729	0	0	0
T26	127079	0	0	0
T27	101423	0	0	0
T28	112064	0	0	0
T29	496289	0	0	0
T30	851415	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2041	0	0
T13	355942	15	0	0
T14	492772	0	0	0
T15	538671	0	0	0
T16	188881	36	0	0
T17	0	18	0	0
T18	0	15	0	0
T19	0	22	0	0
T20	0	22	0	0
T21	0	14	0	0
T22	0	41	0	0
T23	0	40	0	0
T24	0	28	0	0
T25	409729	0	0	0
T26	127079	0	0	0
T27	101423	0	0	0
T28	112064	0	0	0
T29	496289	0	0	0
T30	851415	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2212	0	0
T13	355942	27	0	0
T14	492772	0	0	0
T15	538671	0	0	0
T16	188881	41	0	0
T17	0	28	0	0
T18	0	27	0	0
T19	0	22	0	0
T20	0	18	0	0
T21	0	1	0	0
T22	0	39	0	0
T23	0	32	0	0
T24	0	16	0	0
T25	409729	0	0	0
T26	127079	0	0	0
T27	101423	0	0	0
T28	112064	0	0	0
T29	496289	0	0	0
T30	851415	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2098	0	0
T13	355942	30	0	0
T14	492772	0	0	0
T15	538671	0	0	0
T16	188881	27	0	0
T17	0	25	0	0
T18	0	21	0	0
T19	0	24	0	0
T20	0	10	0	0
T21	0	18	0	0
T22	0	39	0	0
T23	0	40	0	0
T24	0	19	0	0
T25	409729	0	0	0
T26	127079	0	0	0
T27	101423	0	0	0
T28	112064	0	0	0
T29	496289	0	0	0
T30	851415	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2208	0	0
T13	355942	34	0	0
T14	492772	0	0	0
T15	538671	0	0	0
T16	188881	35	0	0
T17	0	13	0	0
T18	0	20	0	0
T19	0	26	0	0
T20	0	22	0	0
T21	0	26	0	0
T22	0	55	0	0
T23	0	39	0	0
T24	0	18	0	0
T25	409729	0	0	0
T26	127079	0	0	0
T27	101423	0	0	0
T28	112064	0	0	0
T29	496289	0	0	0
T30	851415	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1909	0	0
T13	355942	24	0	0
T14	492772	0	0	0
T15	538671	0	0	0
T16	188881	20	0	0
T17	0	8	0	0
T18	0	14	0	0
T19	0	18	0	0
T20	0	20	0	0
T21	0	9	0	0
T22	0	41	0	0
T23	0	46	0	0
T24	0	33	0	0
T25	409729	0	0	0
T26	127079	0	0	0
T27	101423	0	0	0
T28	112064	0	0	0
T29	496289	0	0	0
T30	851415	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2063	0	0
T13	355942	36	0	0
T14	492772	0	0	0
T15	538671	0	0	0
T16	188881	54	0	0
T17	0	27	0	0
T18	0	18	0	0
T19	0	27	0	0
T20	0	15	0	0
T21	0	20	0	0
T22	0	19	0	0
T23	0	44	0	0
T24	0	21	0	0
T25	409729	0	0	0
T26	127079	0	0	0
T27	101423	0	0	0
T28	112064	0	0	0
T29	496289	0	0	0
T30	851415	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1724	0	0
T13	355942	41	0	0
T14	492772	0	0	0
T15	538671	0	0	0
T16	188881	23	0	0
T17	0	26	0	0
T18	0	15	0	0
T19	0	24	0	0
T20	0	12	0	0
T21	0	18	0	0
T22	0	28	0	0
T23	0	29	0	0
T24	0	16	0	0
T25	409729	0	0	0
T26	127079	0	0	0
T27	101423	0	0	0
T28	112064	0	0	0
T29	496289	0	0	0
T30	851415	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1662	0	0
T13	355942	34	0	0
T14	492772	0	0	0
T15	538671	0	0	0
T16	188881	35	0	0
T17	0	43	0	0
T18	0	17	0	0
T19	0	26	0	0
T20	0	14	0	0
T21	0	14	0	0
T22	0	23	0	0
T23	0	33	0	0
T24	0	15	0	0
T25	409729	0	0	0
T26	127079	0	0	0
T27	101423	0	0	0
T28	112064	0	0	0
T29	496289	0	0	0
T30	851415	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2232	0	0
T13	355942	22	0	0
T14	492772	0	0	0
T15	538671	0	0	0
T16	188881	35	0	0
T17	0	20	0	0
T18	0	22	0	0
T19	0	21	0	0
T20	0	19	0	0
T21	0	25	0	0
T22	0	37	0	0
T23	0	25	0	0
T24	0	40	0	0
T25	409729	0	0	0
T26	127079	0	0	0
T27	101423	0	0	0
T28	112064	0	0	0
T29	496289	0	0	0
T30	851415	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1654	0	0
T13	355942	20	0	0
T14	492772	0	0	0
T15	538671	0	0	0
T16	188881	36	0	0
T17	0	30	0	0
T18	0	24	0	0
T19	0	17	0	0
T20	0	24	0	0
T21	0	34	0	0
T22	0	54	0	0
T23	0	26	0	0
T24	0	38	0	0
T25	409729	0	0	0
T26	127079	0	0	0
T27	101423	0	0	0
T28	112064	0	0	0
T29	496289	0	0	0
T30	851415	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1918	0	0
T13	355942	20	0	0
T14	492772	0	0	0
T15	538671	0	0	0
T16	188881	49	0	0
T17	0	23	0	0
T18	0	23	0	0
T19	0	32	0	0
T20	0	13	0	0
T21	0	28	0	0
T22	0	42	0	0
T23	0	40	0	0
T24	0	12	0	0
T25	409729	0	0	0
T26	127079	0	0	0
T27	101423	0	0	0
T28	112064	0	0	0
T29	496289	0	0	0
T30	851415	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1396	0	0
T13	355942	34	0	0
T14	492772	0	0	0
T15	538671	0	0	0
T16	188881	16	0	0
T17	0	31	0	0
T18	0	30	0	0
T19	0	18	0	0
T20	0	13	0	0
T21	0	6	0	0
T22	0	30	0	0
T23	0	33	0	0
T24	0	10	0	0
T25	409729	0	0	0
T26	127079	0	0	0
T27	101423	0	0	0
T28	112064	0	0	0
T29	496289	0	0	0
T30	851415	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1698	0	0
T13	355942	32	0	0
T14	492772	0	0	0
T15	538671	0	0	0
T16	188881	31	0	0
T17	0	17	0	0
T18	0	19	0	0
T19	0	16	0	0
T20	0	25	0	0
T21	0	17	0	0
T22	0	25	0	0
T23	0	32	0	0
T24	0	26	0	0
T25	409729	0	0	0
T26	127079	0	0	0
T27	101423	0	0	0
T28	112064	0	0	0
T29	496289	0	0	0
T30	851415	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2234	0	0
T13	355942	20	0	0
T14	492772	0	0	0
T15	538671	0	0	0
T16	188881	24	0	0
T17	0	24	0	0
T18	0	25	0	0
T19	0	30	0	0
T20	0	31	0	0
T21	0	23	0	0
T22	0	27	0	0
T23	0	59	0	0
T25	409729	0	0	0
T26	127079	0	0	0
T27	101423	0	0	0
T28	112064	0	0	0
T29	496289	0	0	0
T30	851415	0	0	0
T31	0	12	0	0