Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1131147	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1107445

1

T4

3

T1

904

T2

947

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1965477	1			T4	1		T1	1655		T2	1646
values[0x0]	135865	1			T4	1		T1	106		T2	112
values[0x1]	137250	1			T4	3		T1	80		T2	99

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	905744	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1332848

1

T4

3

T1

1080

T2

1167

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6868	1			T1	51		T2	7		T6	4
valid_sources[0x01]	7394	1			T2	4		T6	3		T7	8
valid_sources[0x02]	6727	1			T1	1		T2	11		T3	6
valid_sources[0x03]	6400	1			T2	8		T6	7		T7	7
valid_sources[0x04]	10708	1			T2	14		T6	14		T7	6
valid_sources[0x05]	11672	1			T1	13		T2	11		T6	2
valid_sources[0x06]	11005	1			T1	8		T2	3		T6	4
valid_sources[0x07]	6699	1			T2	4		T3	2		T6	2
valid_sources[0x08]	6973	1			T1	2		T2	10		T3	2
valid_sources[0x09]	7808	1			T1	3		T2	5		T6	9
valid_sources[0x0a]	9027	1			T1	1		T2	6		T3	2
valid_sources[0x0b]	9742	1			T1	6		T2	4		T6	5
valid_sources[0x0c]	15382	1			T1	2		T2	10		T3	5
valid_sources[0x0d]	6690	1			T2	8		T6	29		T7	6
valid_sources[0x0e]	7710	1			T1	6		T2	6		T6	14
valid_sources[0x0f]	9582	1			T1	7		T2	7		T6	6
valid_sources[0x10]	9571	1			T1	8		T2	12		T3	1
valid_sources[0x11]	6699	1			T1	7		T2	8		T6	9
valid_sources[0x12]	6488	1			T1	5		T2	7		T6	4
valid_sources[0x13]	6685	1			T1	2		T2	7		T6	1
valid_sources[0x14]	10976	1			T1	1		T2	9		T6	12
valid_sources[0x15]	7681	1			T2	6		T6	1		T7	8
valid_sources[0x16]	7442	1			T1	4		T2	9		T6	16
valid_sources[0x17]	6456	1			T1	6		T2	8		T6	2
valid_sources[0x18]	7428	1			T1	2		T2	2		T6	3
valid_sources[0x19]	8290	1			T1	2		T2	2		T3	1
valid_sources[0x1a]	11865	1			T1	7		T2	6		T6	13
valid_sources[0x1b]	7741	1			T1	9		T2	13		T6	12
valid_sources[0x1c]	9133	1			T1	1		T2	6		T6	5
valid_sources[0x1d]	6586	1			T1	2		T2	8		T6	2
valid_sources[0x1e]	6454	1			T1	17		T2	8		T6	5
valid_sources[0x1f]	10224	1			T1	5		T2	9		T3	4
valid_sources[0x20]	23688	1			T1	4		T2	9		T6	7
valid_sources[0x21]	6733	1			T1	5		T2	5		T3	5
valid_sources[0x22]	11236	1			T1	8		T2	8		T3	1
valid_sources[0x23]	7024	1			T2	8		T6	4		T7	8
valid_sources[0x24]	10963	1			T1	20		T2	8		T6	9
valid_sources[0x25]	7309	1			T1	4		T2	9		T6	7
valid_sources[0x26]	11455	1			T1	36		T2	8		T6	6
valid_sources[0x27]	6871	1			T1	26		T2	14		T6	45
valid_sources[0x28]	11021	1			T1	2		T2	11		T3	10
valid_sources[0x29]	9346	1			T1	2		T2	6		T6	27
valid_sources[0x2a]	6772	1			T2	6		T3	1		T6	5
valid_sources[0x2b]	6399	1			T1	15		T2	5		T3	9
valid_sources[0x2c]	7402	1			T1	2		T2	9		T6	7
valid_sources[0x2d]	9271	1			T2	5		T6	3		T7	9
valid_sources[0x2e]	6650	1			T1	3		T2	9		T6	2
valid_sources[0x2f]	11211	1			T2	10		T6	95		T7	11
valid_sources[0x30]	7088	1			T2	2		T6	13		T7	4
valid_sources[0x31]	10810	1			T2	7		T6	67		T7	11
valid_sources[0x32]	15688	1			T1	4		T2	8		T3	4
valid_sources[0x33]	7736	1			T1	3		T2	7		T6	9
valid_sources[0x34]	7542	1			T1	3		T2	5		T3	8
valid_sources[0x35]	6519	1			T1	10		T2	4		T3	2
valid_sources[0x36]	7073	1			T1	33		T2	5		T6	1
valid_sources[0x37]	10691	1			T1	3		T2	5		T6	1
valid_sources[0x38]	6607	1			T1	3		T2	5		T6	5
valid_sources[0x39]	7378	1			T2	7		T6	3		T7	4
valid_sources[0x3a]	6994	1			T1	5		T2	12		T6	4
valid_sources[0x3b]	6727	1			T1	3		T2	8		T6	4
valid_sources[0x3c]	15185	1			T1	4		T2	7		T6	3
valid_sources[0x3d]	11133	1			T2	4		T3	5		T6	3
valid_sources[0x3e]	6330	1			T1	1		T2	6		T3	1
valid_sources[0x3f]	6622	1			T1	1		T2	9		T6	2
valid_sources[0x40]	12229	1			T1	2		T2	2		T6	5
valid_sources[0x41]	7538	1			T1	10		T2	6		T3	6
valid_sources[0x42]	6817	1			T1	8		T2	8		T6	1
valid_sources[0x43]	11063	1			T1	32		T2	5		T6	3
valid_sources[0x44]	7285	1			T1	9		T2	9		T3	1
valid_sources[0x45]	8421	1			T1	2		T2	11		T3	7
valid_sources[0x46]	6608	1			T1	2		T2	4		T6	4
valid_sources[0x47]	9501	1			T2	8		T6	14		T7	7
valid_sources[0x48]	13023	1			T1	23		T2	9		T3	3
valid_sources[0x49]	18318	1			T2	10		T3	7		T6	5
valid_sources[0x4a]	15567	1			T1	9		T2	9		T7	4
valid_sources[0x4b]	20708	1			T2	7		T6	3		T7	10
valid_sources[0x4c]	11406	1			T2	7		T6	5		T7	8
valid_sources[0x4d]	11149	1			T1	1		T2	9		T6	7
valid_sources[0x4e]	10818	1			T2	4		T6	3		T7	5
valid_sources[0x4f]	9584	1			T1	27		T2	12		T6	2
valid_sources[0x50]	6546	1			T2	7		T6	4		T7	7
valid_sources[0x51]	6829	1			T2	6		T3	3		T6	14
valid_sources[0x52]	7294	1			T1	2		T2	11		T6	4
valid_sources[0x53]	6761	1			T2	9		T3	3		T6	1
valid_sources[0x54]	9524	1			T4	2		T2	6		T3	5
valid_sources[0x55]	8667	1			T1	2		T2	12		T3	2
valid_sources[0x56]	7016	1			T1	6		T2	9		T3	2
valid_sources[0x57]	11266	1			T1	10		T2	10		T6	47
valid_sources[0x58]	7623	1			T4	1		T2	2		T6	10
valid_sources[0x59]	7203	1			T2	7		T3	6		T6	5
valid_sources[0x5a]	6867	1			T1	14		T2	5		T6	2
valid_sources[0x5b]	6553	1			T2	12		T6	2		T7	2
valid_sources[0x5c]	7575	1			T2	4		T6	6		T7	5
valid_sources[0x5d]	20677	1			T2	11		T3	5		T6	3
valid_sources[0x5e]	7625	1			T1	2		T2	2		T3	6
valid_sources[0x5f]	14878	1			T1	12		T2	6		T6	2
valid_sources[0x60]	14040	1			T1	8		T2	8		T7	10
valid_sources[0x61]	6647	1			T1	9		T2	1		T3	11
valid_sources[0x62]	7586	1			T1	1		T2	13		T6	8
valid_sources[0x63]	7205	1			T2	4		T6	13		T7	7
valid_sources[0x64]	6736	1			T2	6		T6	6		T7	4
valid_sources[0x65]	6847	1			T1	1		T2	10		T6	14
valid_sources[0x66]	10667	1			T2	11		T3	2		T6	17
valid_sources[0x67]	6476	1			T1	15		T2	8		T3	1
valid_sources[0x68]	11870	1			T1	4		T2	3		T3	2
valid_sources[0x69]	6197	1			T1	10		T2	11		T6	15
valid_sources[0x6a]	6293	1			T1	2		T2	8		T6	44
valid_sources[0x6b]	11626	1			T2	5		T6	2		T7	13
valid_sources[0x6c]	7507	1			T1	4		T2	7		T6	4
valid_sources[0x6d]	6573	1			T2	8		T6	15		T7	8
valid_sources[0x6e]	7468	1			T2	11		T6	16		T7	5
valid_sources[0x6f]	6513	1			T1	6		T2	8		T6	7
valid_sources[0x70]	6556	1			T1	1		T2	6		T3	1
valid_sources[0x71]	6749	1			T2	6		T3	1		T6	7
valid_sources[0x72]	10775	1			T1	15		T2	4		T6	4
valid_sources[0x73]	6717	1			T2	6		T6	3		T7	6
valid_sources[0x74]	6743	1			T2	8		T3	5		T6	2
valid_sources[0x75]	7638	1			T2	5		T3	8		T6	1
valid_sources[0x76]	10698	1			T1	7		T2	9		T3	1
valid_sources[0x77]	11302	1			T1	1		T2	6		T6	1
valid_sources[0x78]	9695	1			T1	2		T2	4		T3	10
valid_sources[0x79]	7334	1			T1	3		T2	8		T6	5
valid_sources[0x7a]	10964	1			T2	10		T3	2		T6	3
valid_sources[0x7b]	10062	1			T1	154		T2	13		T6	10
valid_sources[0x7c]	6798	1			T1	1		T2	9		T6	8
valid_sources[0x7d]	7080	1			T2	7		T6	7		T7	4
valid_sources[0x7e]	7627	1			T2	5		T6	2		T7	9
valid_sources[0x7f]	7313	1			T2	9		T3	2		T6	4
valid_sources[0x80]	6334	1			T1	10		T2	6		T6	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

979169

1

T4

1

T1

821

T2

840

values[0x0]

all_enables

biggest_size

74350

1

T1

53

T2

64

T3

21

values[0x1]

all_enables

biggest_size

53926

1

T4

2

T1

30

T2

43