Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	27575	1			T1	16		T2	16		T5	9
auto[PWRUP]	87	1			T9	3		T31	2		T33	5
auto[ONEST_0]	66	1			T7	2		T9	4		T31	2
auto[ONEST_021]	10	1			T7	1		T187	1		T188	1
auto[ONEST_1]	72	1			T7	3		T9	2		T31	2
auto[ONEST_DONE]	2	1			T189	1		T190	1		-	-
auto[LP_0]	123	1			T7	1		T9	4		T31	3
auto[LP_021]	28	1			T9	1		T32	1		T33	1
auto[LP_1]	128	1			T7	1		T9	4		T31	2
auto[LP_EVAL]	51	1			T7	1		T9	6		T31	4
auto[LP_SLP]	465	1			T7	9		T9	13		T31	6
auto[LP_PWRUP]	33	1			T9	1		T32	1		T33	1
auto[NP_0]	116	1			T7	4		T9	7		T31	1
auto[NP_021]	29	1			T9	3		T129	1		T191	1
auto[NP_1]	173	1			T7	3		T9	3		T31	4
auto[NP_EVAL]	26	1			T32	1		T129	1		T158	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T129

1

T192

1

T193

1

min

27175

1

T1

16

T2

16

T5

9

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27182	1			T1	16		T2	16		T5	9
pow[0x1]	3	1			T33	1		T194	1		T195	1
pow[0x2]	13	1			T9	2		T196	1		T192	2
pow[0x3]	29	1			T9	2		T33	3		T197	1
pow[0x4]	53	1			T7	2		T9	1		T197	1
pow[0x5]	109	1			T7	2		T9	4		T32	2
pow[0x6]	221	1			T7	4		T9	8		T31	5
pow[0x7]	464	1			T7	3		T9	14		T31	7

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

170

1

T7

2

T9

6

T31

1

min

26714

1

T1

16

T2

16

T5

9

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	26714	1			T1	16		T2	16		T5	9
pow[0x6]	1	1			T198	1		-	-		-	-
pow[0x7]	3	1			T199	1		T35	1		T200	1
pow[0x8]	1	1			T201	1		-	-		-	-
pow[0x9]	8	1			T32	1		T158	1		T196	1
pow[0xa]	23	1			T9	1		T33	1		T202	1
pow[0xb]	32	1			T9	4		T31	2		T33	1
pow[0xc]	72	1			T9	5		T33	1		T202	1
pow[0xd]	131	1			T7	1		T9	3		T31	5
pow[0xe]	242	1			T7	4		T9	5		T31	1
pow[0xf]	535	1			T7	9		T9	25		T31	8