Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2024	1			T3	10		T7	21		T9	37
auto[PWRUP]	119	1			T7	4		T9	5		T31	4
auto[ONEST_0]	63	1			T3	1		T7	1		T31	1
auto[ONEST_021]	21	1			T31	1		T32	2		T24	1
auto[ONEST_1]	91	1			T3	1		T9	2		T12	1
auto[ONEST_DONE]	10	1			T3	1		T9	2		T196	1
auto[LP_0]	102	1			T3	1		T7	1		T9	4
auto[LP_021]	29	1			T33	1		T197	1		T339	1
auto[LP_1]	116	1			T9	3		T31	5		T32	3
auto[LP_EVAL]	42	1			T7	1		T9	1		T31	1
auto[LP_SLP]	477	1			T7	4		T9	13		T31	10
auto[LP_PWRUP]	26	1			T31	1		T33	1		T202	1
auto[NP_0]	187	1			T3	1		T7	1		T9	2
auto[NP_021]	49	1			T7	1		T9	1		T32	2
auto[NP_1]	168	1			T7	3		T9	3		T12	1
auto[NP_EVAL]	24	1			T9	1		T26	1		T17	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T158

1

T339

1

T80

1

min

1701

1

T3

13

T7

9

T9

21

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1716	1			T3	13		T7	9		T9	23
pow[0x1]	8	1			T32	1		T33	1		T196	1
pow[0x2]	23	1			T9	1		T33	1		T158	1
pow[0x3]	27	1			T32	1		T33	2		T187	1
pow[0x4]	47	1			T9	2		T31	1		T33	1
pow[0x5]	111	1			T9	3		T31	4		T32	3
pow[0x6]	229	1			T7	4		T9	8		T31	6
pow[0x7]	450	1			T3	1		T7	6		T9	10

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

187

1

T7

2

T9

4

T31

1

min

1196

1

T3

11

T7

8

T9

7

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1211	1			T3	11		T7	8		T9	7
pow[0x1]	12	1			T301	2		T151	1		T340	2
pow[0x2]	23	1			T12	1		T15	1		T256	3
pow[0x3]	16	1			T26	2		T27	1		T16	2
pow[0x4]	20	1			T3	1		T16	1		T290	1
pow[0x6]	3	1			T31	1		T341	1		T342	1
pow[0x7]	3	1			T7	1		T343	1		T344	1
pow[0x8]	1	1			T345	1		-	-		-	-
pow[0x9]	9	1			T33	1		T339	2		T80	1
pow[0xa]	23	1			T9	1		T32	1		T158	1
pow[0xb]	31	1			T31	2		T197	1		T187	1
pow[0xc]	77	1			T9	5		T31	1		T32	1
pow[0xd]	123	1			T7	3		T9	6		T31	1
pow[0xe]	276	1			T3	1		T7	5		T9	4
pow[0xf]	537	1			T3	2		T7	8		T9	18