Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1143474	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1121987

1

T1

6

T3

68

T4

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1997805	1			T1	1		T2	1		T3	81
values[0x0]	133475	1			T1	7		T2	1		T3	32
values[0x1]	134181	1			T1	10		T2	1		T3	31

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	915810	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1349651

1

T1

7

T2

2

T3

84

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7331	1			T12	2		T13	7		T26	4
valid_sources[0x01]	6976	1			T3	6		T5	1		T43	1
valid_sources[0x02]	13956	1			T5	1		T43	1		T12	2
valid_sources[0x03]	6743	1			T4	2		T8	2		T13	2
valid_sources[0x04]	6487	1			T12	2		T24	1		T13	1
valid_sources[0x05]	8100	1			T5	1		T42	3		T12	1
valid_sources[0x06]	7703	1			T12	4		T15	2		T16	3
valid_sources[0x07]	10983	1			T5	2		T12	7		T24	1
valid_sources[0x08]	9159	1			T5	2		T12	3		T13	4
valid_sources[0x09]	8142	1			T5	1		T12	2		T24	1
valid_sources[0x0a]	11164	1			T5	3		T12	4		T29	2
valid_sources[0x0b]	12771	1			T22	3		T5	2		T12	5
valid_sources[0x0c]	7097	1			T12	1		T26	4		T30	1
valid_sources[0x0d]	12497	1			T3	1		T11	5		T12	8
valid_sources[0x0e]	22553	1			T3	1		T6	61		T12	4
valid_sources[0x0f]	14105	1			T24	2		T13	3		T26	1
valid_sources[0x10]	8414	1			T5	1		T7	2		T8	1
valid_sources[0x11]	6564	1			T5	1		T24	1		T16	1
valid_sources[0x12]	12841	1			T12	1		T13	1		T26	1
valid_sources[0x13]	6797	1			T14	1		T15	3		T16	6
valid_sources[0x14]	11164	1			T3	4		T5	1		T7	1
valid_sources[0x15]	6718	1			T4	1		T5	1		T53	1
valid_sources[0x16]	9972	1			T5	5		T12	1		T13	4
valid_sources[0x17]	11054	1			T5	4		T12	1		T30	1
valid_sources[0x18]	6598	1			T11	16		T12	7		T24	2
valid_sources[0x19]	7167	1			T5	1		T8	4		T12	3
valid_sources[0x1a]	7610	1			T8	6		T12	4		T24	1
valid_sources[0x1b]	12743	1			T3	1		T5	1		T8	1
valid_sources[0x1c]	6882	1			T5	1		T12	1		T24	1
valid_sources[0x1d]	6866	1			T3	11		T12	5		T13	13
valid_sources[0x1e]	10881	1			T4	1		T5	1		T13	10
valid_sources[0x1f]	8558	1			T22	1		T5	1		T12	2
valid_sources[0x20]	6646	1			T4	4		T5	2		T12	1
valid_sources[0x21]	6840	1			T4	1		T12	3		T13	1
valid_sources[0x22]	7783	1			T5	1		T24	1		T13	1
valid_sources[0x23]	6554	1			T3	4		T5	1		T13	3
valid_sources[0x24]	11596	1			T5	1		T12	13		T26	4
valid_sources[0x25]	6294	1			T5	2		T12	5		T13	2
valid_sources[0x26]	8677	1			T12	5		T13	2		T29	1
valid_sources[0x27]	25159	1			T24	1		T16	3		T47	1
valid_sources[0x28]	6675	1			T43	1		T12	3		T24	2
valid_sources[0x29]	6802	1			T5	1		T12	2		T13	1
valid_sources[0x2a]	6731	1			T8	1		T12	2		T24	1
valid_sources[0x2b]	6351	1			T5	1		T12	1		T24	1
valid_sources[0x2c]	7165	1			T29	1		T15	4		T16	2
valid_sources[0x2d]	9270	1			T3	1		T5	1		T24	2
valid_sources[0x2e]	8508	1			T5	1		T7	1		T12	4
valid_sources[0x2f]	9327	1			T5	3		T12	3		T24	2
valid_sources[0x30]	6644	1			T22	2		T5	2		T8	1
valid_sources[0x31]	6742	1			T12	3		T13	7		T16	7
valid_sources[0x32]	6801	1			T12	4		T15	2		T17	1
valid_sources[0x33]	10997	1			T12	3		T24	1		T13	1
valid_sources[0x34]	7891	1			T8	2		T53	1		T12	5
valid_sources[0x35]	6714	1			T8	8		T12	2		T24	1
valid_sources[0x36]	9529	1			T3	6		T5	1		T8	1
valid_sources[0x37]	8040	1			T4	4		T43	1		T12	6
valid_sources[0x38]	9498	1			T3	6		T5	1		T12	3
valid_sources[0x39]	9396	1			T4	4		T8	2		T13	1
valid_sources[0x3a]	8607	1			T5	1		T13	2		T29	1
valid_sources[0x3b]	11007	1			T8	9		T53	1		T12	2
valid_sources[0x3c]	7867	1			T12	1		T24	1		T13	2
valid_sources[0x3d]	6499	1			T5	2		T12	5		T24	1
valid_sources[0x3e]	6567	1			T24	1		T26	1		T15	5
valid_sources[0x3f]	8589	1			T5	1		T12	5		T26	10
valid_sources[0x40]	7735	1			T12	1		T13	4		T26	1
valid_sources[0x41]	7018	1			T8	2		T12	7		T13	1
valid_sources[0x42]	12283	1			T5	1		T12	3		T15	4
valid_sources[0x43]	7375	1			T8	2		T12	2		T13	1
valid_sources[0x44]	6754	1			T5	1		T12	4		T30	4
valid_sources[0x45]	14872	1			T5	2		T13	4		T15	3
valid_sources[0x46]	8995	1			T43	2		T12	2		T14	2
valid_sources[0x47]	15491	1			T3	9		T12	6		T24	3
valid_sources[0x48]	10721	1			T4	1		T5	1		T7	1
valid_sources[0x49]	6653	1			T8	2		T12	1		T13	4
valid_sources[0x4a]	14072	1			T5	1		T12	6		T24	1
valid_sources[0x4b]	6822	1			T5	2		T7	5		T8	1
valid_sources[0x4c]	7500	1			T3	1		T43	1		T12	7
valid_sources[0x4d]	7076	1			T3	3		T12	2		T30	1
valid_sources[0x4e]	8030	1			T1	18		T12	4		T24	1
valid_sources[0x4f]	6680	1			T5	1		T12	2		T24	1
valid_sources[0x50]	11635	1			T5	1		T24	1		T13	2
valid_sources[0x51]	6884	1			T5	1		T8	1		T12	2
valid_sources[0x52]	6612	1			T5	1		T7	1		T12	2
valid_sources[0x53]	10686	1			T8	3		T12	4		T24	1
valid_sources[0x54]	6727	1			T8	2		T43	1		T12	5
valid_sources[0x55]	9228	1			T4	1		T12	1		T13	6
valid_sources[0x56]	6723	1			T3	4		T5	2		T12	2
valid_sources[0x57]	11187	1			T5	1		T12	4		T29	2
valid_sources[0x58]	10873	1			T5	1		T8	1		T12	3
valid_sources[0x59]	9685	1			T4	1		T12	2		T24	1
valid_sources[0x5a]	6784	1			T5	1		T12	3		T13	2
valid_sources[0x5b]	17713	1			T5	1		T12	1		T13	1
valid_sources[0x5c]	6340	1			T5	1		T12	1		T26	2
valid_sources[0x5d]	6827	1			T7	1		T13	1		T14	4
valid_sources[0x5e]	6973	1			T13	5		T14	10		T15	1
valid_sources[0x5f]	7030	1			T2	3		T12	3		T13	4
valid_sources[0x60]	6998	1			T5	1		T12	2		T13	6
valid_sources[0x61]	7043	1			T8	6		T12	5		T13	1
valid_sources[0x62]	10990	1			T3	4		T8	1		T12	1
valid_sources[0x63]	6784	1			T5	3		T12	2		T13	2
valid_sources[0x64]	6464	1			T5	1		T12	6		T13	4
valid_sources[0x65]	7331	1			T3	1		T5	1		T12	3
valid_sources[0x66]	9739	1			T12	3		T29	1		T15	4
valid_sources[0x67]	7893	1			T22	1		T5	1		T8	3
valid_sources[0x68]	9349	1			T3	7		T4	2		T22	2
valid_sources[0x69]	6825	1			T12	2		T24	1		T15	2
valid_sources[0x6a]	7783	1			T3	1		T5	1		T12	2
valid_sources[0x6b]	10782	1			T12	1		T24	2		T13	2
valid_sources[0x6c]	8520	1			T3	7		T8	2		T12	4
valid_sources[0x6d]	6911	1			T24	1		T13	2		T26	1
valid_sources[0x6e]	12478	1			T5	1		T8	6		T13	1
valid_sources[0x6f]	11394	1			T4	2		T12	1		T13	1
valid_sources[0x70]	6722	1			T12	3		T13	3		T30	1
valid_sources[0x71]	6667	1			T12	1		T13	2		T15	2
valid_sources[0x72]	9545	1			T3	3		T5	1		T43	1
valid_sources[0x73]	6480	1			T5	2		T43	2		T12	5
valid_sources[0x74]	6974	1			T8	3		T12	6		T13	5
valid_sources[0x75]	15468	1			T5	1		T12	1		T24	1
valid_sources[0x76]	7234	1			T3	3		T5	1		T12	2
valid_sources[0x77]	8350	1			T13	1		T29	1		T30	1
valid_sources[0x78]	13442	1			T5	4		T24	4		T13	4
valid_sources[0x79]	6494	1			T7	7		T12	9		T13	1
valid_sources[0x7a]	11083	1			T12	2		T13	1		T30	2
valid_sources[0x7b]	6257	1			T5	5		T12	5		T24	1
valid_sources[0x7c]	7895	1			T23	13		T12	3		T24	1
valid_sources[0x7d]	6769	1			T12	4		T24	1		T13	2
valid_sources[0x7e]	6873	1			T12	3		T24	1		T26	1
valid_sources[0x7f]	6632	1			T4	4		T5	1		T43	1
valid_sources[0x80]	10211	1			T12	4		T24	1		T13	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

995805

1

T3

39

T22

1

T5

81

values[0x0]

all_enables

biggest_size

73502

1

T1

4

T3

21

T4

10

values[0x1]

all_enables

biggest_size

52680

1

T1

2

T3

8

T4

11