Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
84.44	84.44	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	84.44	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	7	38	84.44

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	6	10	62.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	25833	1			T14	9		T16	6		T17	6
auto[PWRUP]	88	1			T57	2		T58	2		T62	1
auto[ONEST_0]	44	1			T58	1		T63	1		T203	1
auto[ONEST_021]	13	1			T58	1		T63	1		T204	1
auto[ONEST_1]	55	1			T57	1		T62	1		T59	2
auto[ONEST_DONE]	5	1			T205	1		T206	1		T207	1
auto[LP_0]	106	1			T57	1		T58	1		T62	5
auto[LP_021]	25	1			T58	1		T63	1		T208	1
auto[LP_1]	104	1			T58	2		T62	1		T60	1
auto[LP_EVAL]	52	1			T58	2		T60	1		T59	1
auto[LP_SLP]	416	1			T57	5		T58	9		T62	5
auto[LP_PWRUP]	17	1			T58	1		T209	1		T210	1
auto[NP_0]	119	1			T57	1		T58	1		T62	1
auto[NP_021]	25	1			T205	1		T204	1		T206	1
auto[NP_1]	136	1			T57	4		T58	5		T60	1
auto[NP_EVAL]	26	1			T57	1		T58	1		T205	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T58

1

T205

1

T211

1

min

25391

1

T14

8

T16

6

T17

6

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	25393	1			T14	8		T16	6		T17	6
pow[0x1]	6	1			T62	2		T208	1		T209	1
pow[0x2]	16	1			T62	1		T212	1		T211	1
pow[0x3]	31	1			T62	1		T60	1		T59	1
pow[0x4]	57	1			T62	1		T205	1		T212	1
pow[0x5]	128	1			T57	2		T58	3		T62	1
pow[0x6]	214	1			T57	2		T58	5		T62	3
pow[0x7]	411	1			T57	12		T58	10		T62	3

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

153

1

T57

1

T58

6

T62

2

min

25009

1

T14

8

T16

6

T17

6

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	6	10	62.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	25010	1			T14	8		T16	6		T17	6
pow[0x7]	2	1			T213	1		T214	1		-	-
pow[0x8]	4	1			T212	1		T211	1		T101	1
pow[0x9]	9	1			T212	1		T215	1		T216	1
pow[0xa]	16	1			T205	2		T61	1		T211	1
pow[0xb]	27	1			T60	1		T205	1		T212	1
pow[0xc]	58	1			T58	2		T62	2		T60	1
pow[0xd]	113	1			T57	3		T58	3		T62	1
pow[0xe]	252	1			T57	5		T58	3		T62	5
pow[0xf]	453	1			T57	7		T58	6		T62	4