Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	1995	1			T2	10		T5	5		T42	20
auto[PWRUP]	127	1			T14	2		T50	1		T57	2
auto[ONEST_0]	76	1			T12	1		T15	1		T49	1
auto[ONEST_021]	17	1			T62	1		T35	1		T203	1
auto[ONEST_1]	85	1			T13	1		T14	1		T50	1
auto[ONEST_DONE]	3	1			T203	1		T92	1		T351	1
auto[LP_0]	113	1			T62	3		T59	2		T205	2
auto[LP_021]	21	1			T14	1		T63	1		T61	1
auto[LP_1]	121	1			T14	1		T57	2		T58	2
auto[LP_EVAL]	40	1			T5	1		T14	1		T57	1
auto[LP_SLP]	401	1			T12	1		T13	1		T14	1
auto[LP_PWRUP]	24	1			T51	1		T60	1		T205	1
auto[NP_0]	156	1			T12	2		T13	2		T14	1
auto[NP_021]	33	1			T12	1		T15	1		T58	2
auto[NP_1]	168	1			T5	1		T12	2		T14	2
auto[NP_EVAL]	15	1			T62	1		T181	1		T33	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

4

1

T352

1

T353

1

T354

2

min

1664

1

T2

10

T5

7

T42

20

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1668	1			T2	10		T5	7		T42	20
pow[0x1]	8	1			T206	1		T330	1		T101	1
pow[0x2]	9	1			T51	1		T58	1		T35	1
pow[0x3]	22	1			T62	2		T208	1		T209	1
pow[0x4]	69	1			T57	1		T62	2		T59	2
pow[0x5]	93	1			T14	1		T57	1		T58	2
pow[0x6]	205	1			T57	3		T58	3		T62	4
pow[0x7]	425	1			T14	2		T57	4		T58	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

169

1

T57

1

T58

2

T62

3

min

1219

1

T2

10

T5

6

T42

20

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1224	1			T2	10		T5	6		T42	20
pow[0x1]	14	1			T5	1		T49	1		T33	1
pow[0x2]	10	1			T14	1		T181	1		T34	1
pow[0x3]	22	1			T12	1		T13	2		T15	4
pow[0x4]	21	1			T12	3		T52	1		T32	1
pow[0x5]	1	1			T210	1		-	-		-	-
pow[0x7]	4	1			T208	1		T355	1		T207	1
pow[0x8]	2	1			T209	1		T356	1		-	-
pow[0x9]	5	1			T357	1		T204	1		T356	1
pow[0xa]	13	1			T205	1		T212	1		T210	1
pow[0xb]	27	1			T57	1		T58	1		T205	1
pow[0xc]	42	1			T13	1		T57	1		T205	1
pow[0xd]	113	1			T57	2		T58	2		T62	3
pow[0xe]	244	1			T57	2		T58	1		T62	3
pow[0xf]	518	1			T14	1		T57	7		T58	8