Unified Coverage Report :: Module :: adc_ctrl_fsm_sva

Module : adc_ctrl_fsm_sva

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_sva_0.1/adc_ctrl_fsm_sva.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva	100.00						100.00

---

Module Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.75	100.00	100.00		100.00	98.73	100.00	u_adc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_fsm_sva

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FsmDebugOut_A	30881658	30807890	0	0
FsmStateHwReset_A	1053	1053	0	0
FsmStateSwReset_A	30881658	6364	0	0
LpSampleCntHwReset_A	1053	1053	0	0
LpSampleCntSwReset_A	30881658	6364	0	0
NpSampleCntHwReset_A	1053	1053	0	0
NpSampleCntSwReset_A	30881658	6364	0	0
PwrupTimerCntHwReset_A	1053	1053	0	0
PwrupTimerCntSwReset_A	30881658	6364	0	0
WakeupTimerCntHwReset_A	1053	1053	0	0
WakeupTimerCntSwReset_A	30881658	6364	0	0

FsmDebugOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30881658	30807890	0	0
T1	78	1	0	0
T2	68	1	0	0
T3	1219	1169	0	0
T4	801	708	0	0
T5	53	1	0	0
T6	1055	997	0	0
T7	675	600	0	0
T8	1105	1052	0	0
T22	77	1	0	0
T23	59	1	0	0

FsmStateHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1053	1053	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

FsmStateSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30881658	6364	0	0
T16	33447	6	0	0
T17	35790	6	0	0
T18	65495	16	0	0
T19	34773	10	0	0
T20	0	6	0	0
T21	0	7	0	0
T31	88	0	0	0
T41	0	16	0	0
T47	6832	0	0	0
T48	944	0	0	0
T54	0	4	0	0
T55	0	15	0	0
T56	60	0	0	0
T88	0	12	0	0
T89	1195	0	0	0
T90	6046	0	0	0

LpSampleCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1053	1053	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

LpSampleCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30881658	6364	0	0
T16	33447	6	0	0
T17	35790	6	0	0
T18	65495	16	0	0
T19	34773	10	0	0
T20	0	6	0	0
T21	0	7	0	0
T31	88	0	0	0
T41	0	16	0	0
T47	6832	0	0	0
T48	944	0	0	0
T54	0	4	0	0
T55	0	15	0	0
T56	60	0	0	0
T88	0	12	0	0
T89	1195	0	0	0
T90	6046	0	0	0

NpSampleCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1053	1053	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

NpSampleCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30881658	6364	0	0
T16	33447	6	0	0
T17	35790	6	0	0
T18	65495	16	0	0
T19	34773	10	0	0
T20	0	6	0	0
T21	0	7	0	0
T31	88	0	0	0
T41	0	16	0	0
T47	6832	0	0	0
T48	944	0	0	0
T54	0	4	0	0
T55	0	15	0	0
T56	60	0	0	0
T88	0	12	0	0
T89	1195	0	0	0
T90	6046	0	0	0

PwrupTimerCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1053	1053	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

PwrupTimerCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30881658	6364	0	0
T16	33447	6	0	0
T17	35790	6	0	0
T18	65495	16	0	0
T19	34773	10	0	0
T20	0	6	0	0
T21	0	7	0	0
T31	88	0	0	0
T41	0	16	0	0
T47	6832	0	0	0
T48	944	0	0	0
T54	0	4	0	0
T55	0	15	0	0
T56	60	0	0	0
T88	0	12	0	0
T89	1195	0	0	0
T90	6046	0	0	0

WakeupTimerCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1053	1053	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

WakeupTimerCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30881658	6364	0	0
T16	33447	6	0	0
T17	35790	6	0	0
T18	65495	16	0	0
T19	34773	10	0	0
T20	0	6	0	0
T21	0	7	0	0
T31	88	0	0	0
T41	0	16	0	0
T47	6832	0	0	0
T48	944	0	0	0
T54	0	4	0	0
T55	0	15	0	0
T56	60	0	0	0
T88	0	12	0	0
T89	1195	0	0	0
T90	6046	0	0	0