Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.83	100.00	99.76		100.00	99.37	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	99.75	100.00	100.00		100.00	98.73	100.00
u_adc_ctrl_intr	99.00	100.00	96.00			100.00	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		63	63	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	213	1	1	100.00

55                      
56         8/8              assign aon_filter_ctl[0][k] = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
57                            min_v: reg2hw_i.adc_chn0_filter_ctl[k].min_v.q,
58                            max_v: reg2hw_i.adc_chn0_filter_ctl[k].max_v.q,
59                            cond:  reg2hw_i.adc_chn0_filter_ctl[k].cond.q,
60                            en:    reg2hw_i.adc_chn0_filter_ctl[k].en.q
61                          };
62                      
63         8/8              assign aon_filter_ctl[1][k] = '{
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
64                            min_v: reg2hw_i.adc_chn1_filter_ctl[k].min_v.q,
65                            max_v: reg2hw_i.adc_chn1_filter_ctl[k].max_v.q,
66                            cond:  reg2hw_i.adc_chn1_filter_ctl[k].cond.q,
67                            en:    reg2hw_i.adc_chn1_filter_ctl[k].en.q
68                          };
69                        end // block: gen_filter_ctl_sync
70                      
71                        // Recent adc channel values
72         1/1            assign adc_chn_val_o[0].adc_chn_value.de = chn0_val_we;
           Tests:       T1 T2 T3 
73         1/1            assign adc_chn_val_o[0].adc_chn_value.d  = chn0_val;
           Tests:       T1 T2 T3 
74         1/1            assign adc_chn_val_o[1].adc_chn_value.de = chn1_val_we;
           Tests:       T1 T2 T3 
75         1/1            assign adc_chn_val_o[1].adc_chn_value.d  = chn1_val;
           Tests:       T1 T2 T3 
76                      
77                        // Interrupt based adc channel values
78                        // The value of the adc is captured whenever an interrupt triggers.
79                        // There are two cases:
80                        // completion of one shot mode
81                        // match detection from the filters
82                        logic chn_val_intr_we;
83         1/1            assign chn_val_intr_we = reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done :
           Tests:       T1 T2 T3 
84                                                 reg2hw_i.adc_en_ctl.adc_enable.q   ? |match_pulse : '0;
85                      
86         1/1            assign adc_chn_val_o[0].adc_chn_value_intr.de = chn_val_intr_we;
           Tests:       T1 T2 T3 
87         1/1            assign adc_chn_val_o[0].adc_chn_value_intr.d  = chn0_val;
           Tests:       T1 T2 T3 
88         1/1            assign adc_chn_val_o[1].adc_chn_value_intr.de = chn_val_intr_we;
           Tests:       T1 T2 T3 
89         1/1            assign adc_chn_val_o[1].adc_chn_value_intr.d  = chn1_val;
           Tests:       T1 T2 T3 
90                      
91                        //Connect the ports for future extension
92                        assign adc_chn_val_o[0].adc_chn_value_ext.de = 1'b0;
93                        assign adc_chn_val_o[0].adc_chn_value_ext.d  = 2'b0;
94                        assign adc_chn_val_o[1].adc_chn_value_ext.de = 1'b0;
95                        assign adc_chn_val_o[1].adc_chn_value_ext.d  = 2'b0;
96                      
97                        assign adc_chn_val_o[0].adc_chn_value_intr_ext.de = 1'b0;
98                        assign adc_chn_val_o[0].adc_chn_value_intr_ext.d  = 2'b0;
99                        assign adc_chn_val_o[1].adc_chn_value_intr_ext.de = 1'b0;
100                       assign adc_chn_val_o[1].adc_chn_value_intr_ext.d  = 2'b0;
101                     
102                       // Evaluate if there is a match from chn0 and chn1 samples
103                       for (genvar k = 0 ; k < NumAdcFilter ; k++) begin : gen_filter_match
104        8/8              assign chn0_match[k] = (!aon_filter_ctl[0][k].cond) ?
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
105                                 (aon_filter_ctl[0][k].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][k].max_v) :
106                                 (aon_filter_ctl[0][k].min_v >  chn0_val) || (chn0_val >  aon_filter_ctl[0][k].max_v);
107        8/8              assign chn1_match[k] = (!aon_filter_ctl[1][k].cond) ?
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
108                                 (aon_filter_ctl[1][k].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][k].max_v) :
109                                 (aon_filter_ctl[1][k].min_v >  chn1_val) || (chn1_val >  aon_filter_ctl[1][k].max_v);
110                     
111                         // If the filter on a particular channel is NOT enabled, it does not participate in the final
112                         // match decision.  This means the match value should have no impact on the final result.
113                         // For example, if channel 0's filter is enabled, but channel 1's is not, the match result
114                         // is determined solely based on whether channel 0's filter shows a match.
115                         // On the other hand, if all channel's filters are enabled, then a match is seen only when
116                         // both filters match.
117        8/8              assign match[k] = |{aon_filter_ctl[0][k].en, aon_filter_ctl[1][k].en} &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
118                                           (!aon_filter_ctl[0][k].en | (chn0_match[k] & aon_filter_ctl[0][k].en)) &
119                                           (!aon_filter_ctl[1][k].en | (chn1_match[k] & aon_filter_ctl[1][k].en)) ;
120                     
121        8/8              assign match_pulse[k] = adc_ctrl_done && match[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
122                     
123                        // Explicitly create assertions for all the matching conditions.
124                        // These assertions are unwieldy and not suitable for expansion to more channels.
125                        // They should be adjusted eventually.
126                        `ASSERT(MatchCheck00_A, !aon_filter_ctl[0][k].en & !aon_filter_ctl[1][k].en |->
127                                !match[k], clk_aon_i, !rst_aon_ni)
128                        `ASSERT(MatchCheck01_A, !aon_filter_ctl[0][k].en & aon_filter_ctl[1][k].en  |->
129                                match[k] == chn1_match[k], clk_aon_i, !rst_aon_ni)
130                        `ASSERT(MatchCheck10_A, aon_filter_ctl[0][k].en & !aon_filter_ctl[1][k].en  |->
131                                match[k] == chn0_match[k], clk_aon_i, !rst_aon_ni)
132                        `ASSERT(MatchCheck11_A, aon_filter_ctl[0][k].en & aon_filter_ctl[1][k].en   |->
133                                match[k] == (chn0_match[k] & chn1_match[k]), clk_aon_i, !rst_aon_ni)
134                       end
135                     
136                       // adc filter status
137        1/1            assign aon_filter_status_o.match.d  = match_pulse | reg2hw_i.filter_status.match.q;
           Tests:       T1 T2 T3 
138        1/1            assign aon_filter_status_o.match.de = |match_pulse;
           Tests:       T1 T2 T3 
139                       // transition status
140        1/1            assign aon_filter_status_o.trans.d  = aon_fsm_trans | reg2hw_i.filter_status.trans.q;
           Tests:       T1 T2 T3 
141        1/1            assign aon_filter_status_o.trans.de = aon_fsm_trans;
           Tests:       T1 T2 T3 
142                     
143                       // generate wakeup to external power manager if filter status
144                       // and wakeup enable are set.
145        1/1            assign wkup_req_o = |(reg2hw_i.filter_status.match.q &
           Tests:       T1 T2 T3 
146                                             reg2hw_i.adc_wakeup_ctl.match_en.q) ||
147                                            (reg2hw_i.filter_status.trans.q &
148                                             reg2hw_i.adc_wakeup_ctl.trans_en.q);
149                     
150                       //instantiate the main state machine
151                       adc_ctrl_fsm u_adc_ctrl_fsm (
152                         .clk_aon_i,
153                         .rst_aon_ni,
154                         // configuration and settings from reg interface
155                         .cfg_fsm_rst_i(reg2hw_i.adc_fsm_rst.q),
156                         .cfg_adc_enable_i(reg2hw_i.adc_en_ctl.adc_enable.q),
157                         .cfg_oneshot_mode_i(reg2hw_i.adc_en_ctl.oneshot_mode.q),
158                         .cfg_lp_mode_i(reg2hw_i.adc_pd_ctl.lp_mode.q),
159                         .cfg_pwrup_time_i(reg2hw_i.adc_pd_ctl.pwrup_time.q),
160                         .cfg_wakeup_time_i(reg2hw_i.adc_pd_ctl.wakeup_time.q),
161                         .cfg_lp_sample_cnt_i(reg2hw_i.adc_lp_sample_ctl.q),
162                         .cfg_np_sample_cnt_i(reg2hw_i.adc_sample_ctl.q),
163                         //
164                         .adc_ctrl_match_i(match),
165                         .adc_d_i(adc_i.data),
166                         .adc_d_val_i(adc_i.data_valid),
167                         .adc_pd_o(adc_o.pd),
168                         .adc_chn_sel_o(adc_o.channel_sel),
169                         .chn0_val_we_o(chn0_val_we),
170                         .chn1_val_we_o(chn1_val_we),
171                         .chn0_val_o(chn0_val),
172                         .chn1_val_o(chn1_val),
173                         .adc_ctrl_done_o(adc_ctrl_done),
174                         .oneshot_done_o(oneshot_done),
175                         .aon_fsm_state_o,
176                         .aon_fsm_trans_o(aon_fsm_trans)
177                       );
178                     
179                       // synchronzie from clk_aon into cfg domain
180                       logic cfg_oneshot_done;
181                       prim_pulse_sync u_oneshot_done_sync (
182                         .clk_src_i(clk_aon_i),
183                         .rst_src_ni(rst_aon_ni),
184                         .src_pulse_i(oneshot_done),
185                         .clk_dst_i(clk_i),
186                         .rst_dst_ni(rst_ni),
187                         .dst_pulse_o(cfg_oneshot_done)
188                       );
189                     
190                       //Instantiate the interrupt module
191                       adc_ctrl_intr u_adc_ctrl_intr (
192                         .clk_i,
193                         .rst_ni,
194                         .clk_aon_i,
195                         .rst_aon_ni,
196                         .aon_filter_match_i(match_pulse),
197                         .aon_fsm_trans_i(aon_fsm_trans),
198                         .cfg_oneshot_done_i(cfg_oneshot_done),
199                         .cfg_intr_en_i(reg2hw_i.adc_intr_ctl.match_en.q),
200                         .cfg_intr_trans_en_i(reg2hw_i.adc_intr_ctl.trans_en.q),
201                         .cfg_oneshot_done_en_i(reg2hw_i.adc_intr_ctl.oneshot_en.q),
202                         .intr_state_i(reg2hw_i.intr_state),
203                         .intr_enable_i(reg2hw_i.intr_enable),
204                         .intr_test_i(reg2hw_i.intr_test),
205                         .intr_state_o,
206                         .adc_intr_status_i(reg2hw_i.adc_intr_status),
207                         .adc_intr_status_o,
208                         .intr_o
209                       );
210                     
211                       // unused register inputs
212                       logic unused_cfgs;
213        1/1            assign unused_cfgs = ^reg2hw_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	293	293	100.00
Logical	293	293	100.00
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
83-121	100.00
121-145	100.00

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	83	3	3	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00

83           assign chn_val_intr_we = reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done :
                                                                         -1-  
                                                                         ==>  
84                                    reg2hw_i.adc_en_ctl.adc_enable.q   ? |match_pulse : '0;
                                                                         -2-  
                                                                         ==>  
                                                                         ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

104            assign chn0_match[k] = (!aon_filter_ctl[0][k].cond) ?
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T12,T13

107            assign chn1_match[k] = (!aon_filter_ctl[1][k].cond) ?
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T12,T14,T31

104            assign chn0_match[k] = (!aon_filter_ctl[0][k].cond) ?
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T15,T17

107            assign chn1_match[k] = (!aon_filter_ctl[1][k].cond) ?
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T15,T17

104            assign chn0_match[k] = (!aon_filter_ctl[0][k].cond) ?
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T13,T17

107            assign chn1_match[k] = (!aon_filter_ctl[1][k].cond) ?
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T13,T15

104            assign chn0_match[k] = (!aon_filter_ctl[0][k].cond) ?
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T15,T17,T19

107            assign chn1_match[k] = (!aon_filter_ctl[1][k].cond) ?
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T15,T17,T19

104            assign chn0_match[k] = (!aon_filter_ctl[0][k].cond) ?
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T31,T19

107            assign chn1_match[k] = (!aon_filter_ctl[1][k].cond) ?
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T31,T19

104            assign chn0_match[k] = (!aon_filter_ctl[0][k].cond) ?
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T12,T13,T14

107            assign chn1_match[k] = (!aon_filter_ctl[1][k].cond) ?
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T12,T13,T14

104            assign chn0_match[k] = (!aon_filter_ctl[0][k].cond) ?
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T13,T17,T19

107            assign chn1_match[k] = (!aon_filter_ctl[1][k].cond) ?
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T13,T17,T19

104            assign chn0_match[k] = (!aon_filter_ctl[0][k].cond) ?
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T14,T16

107            assign chn1_match[k] = (!aon_filter_ctl[1][k].cond) ?
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T14,T16

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	32348746	32088822	0	0
gen_filter_match[0].MatchCheck00_A	32348746	9125603	0	0
gen_filter_match[0].MatchCheck01_A	32348746	2535099	0	0
gen_filter_match[0].MatchCheck10_A	32348746	2494547	0	0
gen_filter_match[0].MatchCheck11_A	32348746	17933573	0	0
gen_filter_match[1].MatchCheck00_A	32348746	10631242	0	0
gen_filter_match[1].MatchCheck01_A	32348746	1100414	0	0
gen_filter_match[1].MatchCheck10_A	32348746	1194558	0	0
gen_filter_match[1].MatchCheck11_A	32348746	19162608	0	0
gen_filter_match[2].MatchCheck00_A	32348746	11295324	0	0
gen_filter_match[2].MatchCheck01_A	32348746	581456	0	0
gen_filter_match[2].MatchCheck10_A	32348746	527505	0	0
gen_filter_match[2].MatchCheck11_A	32348746	19684537	0	0
gen_filter_match[3].MatchCheck00_A	32348746	11246292	0	0
gen_filter_match[3].MatchCheck01_A	32348746	305269	0	0
gen_filter_match[3].MatchCheck10_A	32348746	143539	0	0
gen_filter_match[3].MatchCheck11_A	32348746	20393722	0	0
gen_filter_match[4].MatchCheck00_A	32348746	12111018	0	0
gen_filter_match[4].MatchCheck01_A	32348746	35188	0	0
gen_filter_match[4].MatchCheck10_A	32348746	34120	0	0
gen_filter_match[4].MatchCheck11_A	32348746	19908496	0	0
gen_filter_match[5].MatchCheck00_A	32348746	11730015	0	0
gen_filter_match[5].MatchCheck01_A	32348746	16	0	0
gen_filter_match[5].MatchCheck10_A	32348746	35200	0	0
gen_filter_match[5].MatchCheck11_A	32348746	20323591	0	0
gen_filter_match[6].MatchCheck00_A	32348746	11989679	0	0
gen_filter_match[6].MatchCheck01_A	32348746	134202	0	0
gen_filter_match[6].MatchCheck10_A	32348746	106	0	0
gen_filter_match[6].MatchCheck11_A	32348746	19964835	0	0
gen_filter_match[7].MatchCheck00_A	32348746	11632163	0	0
gen_filter_match[7].MatchCheck01_A	32348746	236109	0	0
gen_filter_match[7].MatchCheck10_A	32348746	65887	0	0
gen_filter_match[7].MatchCheck11_A	32348746	20154663	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32348746	32088822	0	0
T1	81	4	0	0
T2	770	16	0	0
T3	1219	1169	0	0
T4	801	708	0	0
T5	510	182	0	0
T6	1055	997	0	0
T7	675	600	0	0
T8	1105	1052	0	0
T22	106	30	0	0
T23	63	5	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32348746	9125603	0	0
T1	81	4	0	0
T2	770	16	0	0
T3	1219	1169	0	0
T4	801	708	0	0
T5	510	66	0	0
T6	1055	997	0	0
T7	675	600	0	0
T8	1105	1052	0	0
T22	106	30	0	0
T23	63	5	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32348746	2535099	0	0
T49	791	0	0	0
T69	0	36017	0	0
T78	779	0	0	0
T79	0	31104	0	0
T135	82244	1	0	0
T137	67038	0	0	0
T138	43834	0	0	0
T139	0	33141	0	0
T140	0	32775	0	0
T141	0	1	0	0
T142	0	32871	0	0
T143	0	31921	0	0
T144	0	36461	0	0
T145	0	32700	0	0
T146	81	0	0	0
T147	1126	0	0	0
T148	32502	0	0	0
T149	991	0	0	0
T150	32919	0	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32348746	2494547	0	0
T12	6061	4	0	0
T13	5187	0	0	0
T14	11067	0	0	0
T16	0	3	0	0
T17	0	35736	0	0
T18	0	2	0	0
T24	1186	0	0	0
T25	850	0	0	0
T26	12637	0	0	0
T27	1167	0	0	0
T28	75	0	0	0
T29	859	0	0	0
T30	7997	0	0	0
T41	0	33870	0	0
T55	0	34193	0	0
T68	0	33997	0	0
T88	0	1	0	0
T135	0	1	0	0
T137	0	1	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32348746	17933573	0	0
T5	510	116	0	0
T6	1055	0	0	0
T7	675	0	0	0
T8	1105	0	0	0
T9	1185	0	0	0
T10	1070	0	0	0
T11	7368	0	0	0
T12	0	2946	0	0
T13	0	123	0	0
T14	0	694	0	0
T16	0	33376	0	0
T18	0	65419	0	0
T19	0	34719	0	0
T21	0	33312	0	0
T23	63	0	0	0
T42	1696	0	0	0
T43	85	0	0	0
T55	0	32017	0	0
T88	0	82064	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32348746	10631242	0	0
T1	81	4	0	0
T2	770	16	0	0
T3	1219	1169	0	0
T4	801	708	0	0
T5	510	66	0	0
T6	1055	997	0	0
T7	675	600	0	0
T8	1105	1052	0	0
T22	106	30	0	0
T23	63	5	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32348746	1100414	0	0
T41	70788	1	0	0
T49	791	0	0	0
T54	32798	0	0	0
T55	66280	0	0	0
T68	0	33895	0	0
T88	82130	0	0	0
T135	82244	1	0	0
T137	67038	0	0	0
T144	0	32231	0	0
T146	81	0	0	0
T151	0	38530	0	0
T152	0	33605	0	0
T153	0	2	0	0
T154	0	33626	0	0
T155	0	32698	0	0
T156	0	33381	0	0
T157	920	0	0	0
T158	5720	0	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32348746	1194558	0	0
T16	33447	3	0	0
T17	35790	0	0	0
T18	65495	2	0	0
T19	34773	0	0	0
T31	519	0	0	0
T32	0	2	0	0
T41	0	1	0	0
T47	6832	0	0	0
T48	944	0	0	0
T51	0	1460	0	0
T56	72	0	0	0
T88	0	1	0	0
T89	1195	0	0	0
T90	6046	0	0	0
T135	0	1	0	0
T138	0	1	0	0
T159	0	32411	0	0
T160	0	65869	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32348746	19162608	0	0
T5	510	116	0	0
T6	1055	0	0	0
T7	675	0	0	0
T8	1105	0	0	0
T9	1185	0	0	0
T10	1070	0	0	0
T11	7368	0	0	0
T16	0	33376	0	0
T17	0	35736	0	0
T18	0	65419	0	0
T19	0	34719	0	0
T23	63	0	0	0
T41	0	36823	0	0
T42	1696	0	0	0
T43	85	0	0	0
T88	0	82064	0	0
T135	0	49564	0	0
T138	0	43733	0	0
T148	0	32448	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32348746	11295324	0	0
T1	81	4	0	0
T2	770	16	0	0
T3	1219	1169	0	0
T4	801	708	0	0
T5	510	66	0	0
T6	1055	997	0	0
T7	675	600	0	0
T8	1105	1052	0	0
T22	106	30	0	0
T23	63	5	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32348746	581456	0	0
T15	2333	1143	0	0
T16	33447	0	0	0
T17	35790	0	0	0
T18	65495	0	0	0
T31	519	0	0	0
T32	0	536	0	0
T46	6847	0	0	0
T47	6832	0	0	0
T48	944	0	0	0
T56	72	0	0	0
T89	1195	0	0	0
T160	0	1	0	0
T161	0	32442	0	0
T162	0	1	0	0
T163	0	37107	0	0
T164	0	32561	0	0
T165	0	1	0	0
T166	0	2	0	0
T167	0	33391	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32348746	527505	0	0
T12	6061	4	0	0
T13	5187	0	0	0
T14	11067	7617	0	0
T16	0	3	0	0
T17	0	1	0	0
T18	0	2	0	0
T20	0	1	0	0
T24	1186	0	0	0
T25	850	0	0	0
T26	12637	0	0	0
T27	1167	0	0	0
T28	75	0	0	0
T29	859	0	0	0
T30	7997	0	0	0
T41	0	1	0	0
T55	0	1	0	0
T88	0	1	0	0
T137	0	1	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32348746	19684537	0	0
T5	510	116	0	0
T6	1055	0	0	0
T7	675	0	0	0
T8	1105	0	0	0
T9	1185	0	0	0
T10	1070	0	0	0
T11	7368	0	0	0
T12	0	2946	0	0
T16	0	33376	0	0
T17	0	35735	0	0
T18	0	65419	0	0
T20	0	33325	0	0
T23	63	0	0	0
T41	0	70693	0	0
T42	1696	0	0	0
T43	85	0	0	0
T55	0	34192	0	0
T88	0	82064	0	0
T137	0	32622	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32348746	11246292	0	0
T1	81	4	0	0
T2	770	16	0	0
T3	1219	1169	0	0
T4	801	708	0	0
T5	510	182	0	0
T6	1055	997	0	0
T7	675	600	0	0
T8	1105	1052	0	0
T22	106	30	0	0
T23	63	5	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32348746	305269	0	0
T41	70788	1	0	0
T49	791	0	0	0
T54	32798	0	0	0
T55	66280	0	0	0
T68	0	40677	0	0
T88	82130	0	0	0
T135	82244	0	0	0
T137	67038	1	0	0
T146	81	0	0	0
T153	0	3	0	0
T154	0	35181	0	0
T155	0	1	0	0
T157	920	0	0	0
T158	5720	0	0	0
T165	0	1	0	0
T168	0	32987	0	0
T169	0	58987	0	0
T170	0	32417	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32348746	143539	0	0
T12	6061	4	0	0
T13	5187	0	0	0
T14	11067	0	0	0
T16	0	2	0	0
T17	0	1	0	0
T18	0	2	0	0
T19	0	1	0	0
T20	0	1	0	0
T24	1186	0	0	0
T25	850	0	0	0
T26	12637	0	0	0
T27	1167	0	0	0
T28	75	0	0	0
T29	859	0	0	0
T30	7997	0	0	0
T41	0	1	0	0
T88	0	1	0	0
T135	0	2	0	0
T137	0	1	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32348746	20393722	0	0
T12	6061	2946	0	0
T13	5187	0	0	0
T14	11067	0	0	0
T15	0	1143	0	0
T16	0	33376	0	0
T17	0	35735	0	0
T18	0	65418	0	0
T19	0	34718	0	0
T20	0	33325	0	0
T24	1186	0	0	0
T25	850	0	0	0
T26	12637	0	0	0
T27	1167	0	0	0
T28	75	0	0	0
T29	859	0	0	0
T30	7997	0	0	0
T41	0	36823	0	0
T88	0	82064	0	0
T135	0	82148	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32348746	12111018	0	0
T1	81	4	0	0
T2	770	16	0	0
T3	1219	1169	0	0
T4	801	708	0	0
T5	510	182	0	0
T6	1055	997	0	0
T7	675	600	0	0
T8	1105	1052	0	0
T22	106	30	0	0
T23	63	5	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32348746	35188	0	0
T110	0	35175	0	0
T144	104631	1	0	0
T155	0	1	0	0
T162	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0
T173	0	3	0	0
T174	0	3	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	99319	0	0	0
T178	78815	0	0	0
T179	32331	0	0	0
T180	32321	0	0	0
T181	545	0	0	0
T182	104	0	0	0
T183	968	0	0	0
T184	66238	0	0	0
T185	65385	0	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32348746	34120	0	0
T16	33447	2	0	0
T17	35790	0	0	0
T18	65495	2	0	0
T19	34773	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T31	519	0	0	0
T41	0	1	0	0
T47	6832	0	0	0
T48	944	0	0	0
T55	0	1	0	0
T56	72	0	0	0
T88	0	1	0	0
T89	1195	0	0	0
T90	6046	0	0	0
T135	0	2	0	0
T137	0	1	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32348746	19908496	0	0
T13	5187	3916	0	0
T14	11067	0	0	0
T15	2333	0	0	0
T16	0	33376	0	0
T18	0	65418	0	0
T19	0	34718	0	0
T20	0	33325	0	0
T21	0	33311	0	0
T26	12637	0	0	0
T27	1167	0	0	0
T28	75	0	0	0
T29	859	0	0	0
T30	7997	0	0	0
T41	0	70693	0	0
T44	1515	0	0	0
T45	1166	0	0	0
T55	0	66209	0	0
T88	0	82064	0	0
T135	0	82148	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32348746	11730015	0	0
T1	81	4	0	0
T2	770	16	0	0
T3	1219	1169	0	0
T4	801	708	0	0
T5	510	182	0	0
T6	1055	997	0	0
T7	675	600	0	0
T8	1105	1052	0	0
T22	106	30	0	0
T23	63	5	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32348746	16	0	0
T41	70788	1	0	0
T49	791	0	0	0
T54	32798	0	0	0
T55	66280	0	0	0
T88	82130	0	0	0
T135	82244	0	0	0
T137	67038	0	0	0
T144	0	2	0	0
T146	81	0	0	0
T151	0	1	0	0
T153	0	2	0	0
T155	0	1	0	0
T157	920	0	0	0
T158	5720	0	0	0
T162	0	1	0	0
T166	0	2	0	0
T171	0	1	0	0
T172	0	1	0	0
T186	0	1	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32348746	35200	0	0
T16	33447	3	0	0
T17	35790	0	0	0
T18	65495	2	0	0
T19	34773	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T31	519	0	0	0
T41	0	1	0	0
T47	6832	0	0	0
T48	944	0	0	0
T56	72	0	0	0
T69	0	1	0	0
T88	0	2	0	0
T89	1195	0	0	0
T90	6046	0	0	0
T137	0	1	0	0
T141	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32348746	20323591	0	0
T13	5187	3916	0	0
T14	11067	0	0	0
T15	2333	0	0	0
T16	0	33375	0	0
T18	0	65418	0	0
T19	0	34718	0	0
T20	0	33325	0	0
T21	0	33311	0	0
T26	12637	0	0	0
T27	1167	0	0	0
T28	75	0	0	0
T29	859	0	0	0
T30	7997	0	0	0
T41	0	36823	0	0
T44	1515	0	0	0
T45	1166	0	0	0
T54	0	32697	0	0
T88	0	82063	0	0
T137	0	32622	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32348746	11989679	0	0
T1	81	4	0	0
T2	770	16	0	0
T3	1219	1169	0	0
T4	801	708	0	0
T5	510	66	0	0
T6	1055	997	0	0
T7	675	600	0	0
T8	1105	1052	0	0
T22	106	30	0	0
T23	63	5	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32348746	134202	0	0
T12	6061	2944	0	0
T13	5187	0	0	0
T14	11067	0	0	0
T24	1186	0	0	0
T25	850	0	0	0
T26	12637	0	0	0
T27	1167	0	0	0
T28	75	0	0	0
T29	859	0	0	0
T30	7997	0	0	0
T98	0	31883	0	0
T151	0	1	0	0
T166	0	1	0	0
T187	0	34435	0	0
T188	0	1	0	0
T189	0	1	0	0
T190	0	32732	0	0
T191	0	1	0	0
T192	0	32202	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32348746	106	0	0
T16	33447	2	0	0
T17	35790	0	0	0
T18	65495	2	0	0
T19	34773	0	0	0
T20	0	1	0	0
T31	519	0	0	0
T41	0	1	0	0
T47	6832	0	0	0
T48	944	0	0	0
T55	0	2	0	0
T56	72	0	0	0
T88	0	1	0	0
T89	1195	0	0	0
T90	6046	0	0	0
T135	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T193	0	1	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32348746	19964835	0	0
T5	510	116	0	0
T6	1055	0	0	0
T7	675	0	0	0
T8	1105	0	0	0
T9	1185	0	0	0
T10	1070	0	0	0
T11	7368	0	0	0
T15	0	1143	0	0
T16	0	33375	0	0
T18	0	65418	0	0
T20	0	33325	0	0
T23	63	0	0	0
T41	0	33868	0	0
T42	1696	0	0	0
T43	85	0	0	0
T54	0	32697	0	0
T55	0	34191	0	0
T88	0	82063	0	0
T135	0	32583	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32348746	11632163	0	0
T1	81	4	0	0
T2	770	16	0	0
T3	1219	1169	0	0
T4	801	708	0	0
T5	510	182	0	0
T6	1055	997	0	0
T7	675	600	0	0
T8	1105	1052	0	0
T22	106	30	0	0
T23	63	5	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32348746	236109	0	0
T69	71151	1	0	0
T151	104260	1	0	0
T155	0	1	0	0
T160	65964	0	0	0
T161	32535	0	0	0
T171	0	1	0	0
T172	0	1	0	0
T188	0	1	0	0
T190	0	1	0	0
T194	0	41341	0	0
T195	0	32652	0	0
T196	0	32456	0	0
T197	38514	0	0	0
T198	80	0	0	0
T199	32405	0	0	0
T200	67164	0	0	0
T201	8218	0	0	0
T202	1184	0	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32348746	65887	0	0
T12	6061	5	0	0
T13	5187	0	0	0
T14	11067	0	0	0
T16	0	2	0	0
T17	0	1	0	0
T18	0	1	0	0
T24	1186	0	0	0
T25	850	0	0	0
T26	12637	0	0	0
T27	1167	0	0	0
T28	75	0	0	0
T29	859	0	0	0
T30	7997	0	0	0
T41	0	1	0	0
T55	0	2	0	0
T69	0	1	0	0
T88	0	1	0	0
T137	0	1	0	0
T193	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32348746	20154663	0	0
T12	6061	2943	0	0
T13	5187	3916	0	0
T14	11067	0	0	0
T15	0	1143	0	0
T16	0	33375	0	0
T17	0	35735	0	0
T18	0	65418	0	0
T24	1186	0	0	0
T25	850	0	0	0
T26	12637	0	0	0
T27	1167	0	0	0
T28	75	0	0	0
T29	859	0	0	0
T30	7997	0	0	0
T41	0	33868	0	0
T55	0	66208	0	0
T88	0	82063	0	0
T137	0	32622	0	0