Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2077	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2063	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1964	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2137	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2122	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2052	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1943	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1979	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2123	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2117	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2111	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1892	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1988	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2081	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2189	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2187	0	0
adc_en_ctl_rd_A	2147483647	1606	0	0
adc_fsm_rst_rd_A	2147483647	1643	0	0
adc_intr_ctl_rd_A	2147483647	1915	0	0
adc_lp_sample_ctl_rd_A	2147483647	1688	0	0
adc_pd_ctl_rd_A	2147483647	1878	0	0
adc_sample_ctl_rd_A	2147483647	1500	0	0
adc_wakeup_ctl_rd_A	2147483647	1794	0	0
intr_enable_rd_A	2147483647	2026	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2077	0	0
T12	485034	36	0	0
T13	393091	0	0	0
T14	595340	0	0	0
T24	148498	0	0	0
T25	174668	0	0	0
T26	821468	0	0	0
T27	583962	0	0	0
T28	18603	0	0	0
T29	412987	0	0	0
T30	959815	0	0	0
T31	0	51	0	0
T32	0	27	0	0
T33	0	20	0	0
T34	0	32	0	0
T35	0	18	0	0
T36	0	38	0	0
T37	0	34	0	0
T38	0	20	0	0
T39	0	38	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2063	0	0
T12	485034	43	0	0
T13	393091	0	0	0
T14	595340	0	0	0
T24	148498	0	0	0
T25	174668	0	0	0
T26	821468	0	0	0
T27	583962	0	0	0
T28	18603	0	0	0
T29	412987	0	0	0
T30	959815	0	0	0
T31	0	38	0	0
T32	0	21	0	0
T33	0	10	0	0
T34	0	12	0	0
T35	0	32	0	0
T36	0	21	0	0
T37	0	33	0	0
T38	0	22	0	0
T39	0	44	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1964	0	0
T12	485034	32	0	0
T13	393091	0	0	0
T14	595340	0	0	0
T24	148498	0	0	0
T25	174668	0	0	0
T26	821468	0	0	0
T27	583962	0	0	0
T28	18603	0	0	0
T29	412987	0	0	0
T30	959815	0	0	0
T31	0	31	0	0
T32	0	17	0	0
T33	0	28	0	0
T34	0	32	0	0
T35	0	17	0	0
T36	0	15	0	0
T37	0	27	0	0
T38	0	23	0	0
T39	0	38	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2137	0	0
T12	485034	37	0	0
T13	393091	0	0	0
T14	595340	0	0	0
T24	148498	0	0	0
T25	174668	0	0	0
T26	821468	0	0	0
T27	583962	0	0	0
T28	18603	0	0	0
T29	412987	0	0	0
T30	959815	0	0	0
T31	0	46	0	0
T32	0	10	0	0
T33	0	11	0	0
T34	0	30	0	0
T35	0	26	0	0
T36	0	14	0	0
T37	0	56	0	0
T38	0	12	0	0
T39	0	48	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2122	0	0
T12	485034	31	0	0
T13	393091	0	0	0
T14	595340	0	0	0
T24	148498	0	0	0
T25	174668	0	0	0
T26	821468	0	0	0
T27	583962	0	0	0
T28	18603	0	0	0
T29	412987	0	0	0
T30	959815	0	0	0
T31	0	34	0	0
T32	0	21	0	0
T33	0	37	0	0
T34	0	15	0	0
T35	0	27	0	0
T36	0	17	0	0
T37	0	44	0	0
T38	0	20	0	0
T39	0	37	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2052	0	0
T12	485034	31	0	0
T13	393091	0	0	0
T14	595340	0	0	0
T24	148498	0	0	0
T25	174668	0	0	0
T26	821468	0	0	0
T27	583962	0	0	0
T28	18603	0	0	0
T29	412987	0	0	0
T30	959815	0	0	0
T31	0	38	0	0
T32	0	27	0	0
T33	0	9	0	0
T34	0	11	0	0
T35	0	22	0	0
T36	0	25	0	0
T37	0	38	0	0
T38	0	18	0	0
T39	0	41	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1943	0	0
T12	485034	28	0	0
T13	393091	0	0	0
T14	595340	0	0	0
T24	148498	0	0	0
T25	174668	0	0	0
T26	821468	0	0	0
T27	583962	0	0	0
T28	18603	0	0	0
T29	412987	0	0	0
T30	959815	0	0	0
T31	0	35	0	0
T32	0	22	0	0
T33	0	6	0	0
T34	0	25	0	0
T35	0	34	0	0
T36	0	14	0	0
T37	0	31	0	0
T38	0	21	0	0
T39	0	51	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1979	0	0
T12	485034	33	0	0
T13	393091	0	0	0
T14	595340	0	0	0
T24	148498	0	0	0
T25	174668	0	0	0
T26	821468	0	0	0
T27	583962	0	0	0
T28	18603	0	0	0
T29	412987	0	0	0
T30	959815	0	0	0
T31	0	33	0	0
T32	0	20	0	0
T33	0	13	0	0
T34	0	16	0	0
T35	0	24	0	0
T36	0	11	0	0
T37	0	37	0	0
T38	0	24	0	0
T39	0	38	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2123	0	0
T12	485034	43	0	0
T13	393091	0	0	0
T14	595340	0	0	0
T24	148498	0	0	0
T25	174668	0	0	0
T26	821468	0	0	0
T27	583962	0	0	0
T28	18603	0	0	0
T29	412987	0	0	0
T30	959815	0	0	0
T31	0	43	0	0
T32	0	11	0	0
T33	0	24	0	0
T34	0	16	0	0
T35	0	17	0	0
T36	0	22	0	0
T37	0	26	0	0
T38	0	20	0	0
T39	0	64	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2117	0	0
T12	485034	33	0	0
T13	393091	0	0	0
T14	595340	0	0	0
T24	148498	0	0	0
T25	174668	0	0	0
T26	821468	0	0	0
T27	583962	0	0	0
T28	18603	0	0	0
T29	412987	0	0	0
T30	959815	0	0	0
T31	0	37	0	0
T32	0	20	0	0
T33	0	23	0	0
T34	0	7	0	0
T35	0	11	0	0
T36	0	20	0	0
T37	0	31	0	0
T38	0	29	0	0
T39	0	26	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2111	0	0
T12	485034	47	0	0
T13	393091	0	0	0
T14	595340	0	0	0
T24	148498	0	0	0
T25	174668	0	0	0
T26	821468	0	0	0
T27	583962	0	0	0
T28	18603	0	0	0
T29	412987	0	0	0
T30	959815	0	0	0
T31	0	27	0	0
T32	0	27	0	0
T33	0	25	0	0
T34	0	17	0	0
T35	0	21	0	0
T36	0	20	0	0
T37	0	22	0	0
T38	0	28	0	0
T39	0	46	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1892	0	0
T12	485034	56	0	0
T13	393091	0	0	0
T14	595340	0	0	0
T24	148498	0	0	0
T25	174668	0	0	0
T26	821468	0	0	0
T27	583962	0	0	0
T28	18603	0	0	0
T29	412987	0	0	0
T30	959815	0	0	0
T31	0	42	0	0
T32	0	13	0	0
T33	0	9	0	0
T34	0	18	0	0
T35	0	15	0	0
T36	0	17	0	0
T37	0	18	0	0
T38	0	26	0	0
T39	0	33	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1988	0	0
T12	485034	36	0	0
T13	393091	0	0	0
T14	595340	0	0	0
T24	148498	0	0	0
T25	174668	0	0	0
T26	821468	0	0	0
T27	583962	0	0	0
T28	18603	0	0	0
T29	412987	0	0	0
T30	959815	0	0	0
T31	0	31	0	0
T32	0	27	0	0
T33	0	19	0	0
T34	0	6	0	0
T35	0	16	0	0
T36	0	12	0	0
T37	0	37	0	0
T38	0	26	0	0
T39	0	44	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2081	0	0
T12	485034	50	0	0
T13	393091	0	0	0
T14	595340	0	0	0
T24	148498	0	0	0
T25	174668	0	0	0
T26	821468	0	0	0
T27	583962	0	0	0
T28	18603	0	0	0
T29	412987	0	0	0
T30	959815	0	0	0
T31	0	34	0	0
T32	0	23	0	0
T33	0	11	0	0
T34	0	22	0	0
T35	0	19	0	0
T36	0	12	0	0
T37	0	26	0	0
T38	0	21	0	0
T39	0	51	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2189	0	0
T12	485034	20	0	0
T13	393091	0	0	0
T14	595340	0	0	0
T24	148498	0	0	0
T25	174668	0	0	0
T26	821468	0	0	0
T27	583962	0	0	0
T28	18603	0	0	0
T29	412987	0	0	0
T30	959815	0	0	0
T31	0	32	0	0
T32	0	17	0	0
T33	0	9	0	0
T34	0	28	0	0
T35	0	14	0	0
T36	0	14	0	0
T37	0	50	0	0
T38	0	7	0	0
T39	0	38	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2187	0	0
T12	485034	33	0	0
T13	393091	0	0	0
T14	595340	0	0	0
T24	148498	0	0	0
T25	174668	0	0	0
T26	821468	0	0	0
T27	583962	0	0	0
T28	18603	0	0	0
T29	412987	0	0	0
T30	959815	0	0	0
T31	0	43	0	0
T32	0	12	0	0
T33	0	27	0	0
T34	0	23	0	0
T35	0	23	0	0
T36	0	12	0	0
T37	0	42	0	0
T38	0	21	0	0
T39	0	35	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1606	0	0
T12	485034	43	0	0
T13	393091	0	0	0
T14	595340	0	0	0
T24	148498	0	0	0
T25	174668	0	0	0
T26	821468	0	0	0
T27	583962	0	0	0
T28	18603	0	0	0
T29	412987	0	0	0
T30	959815	0	0	0
T31	0	38	0	0
T32	0	8	0	0
T33	0	11	0	0
T34	0	7	0	0
T35	0	23	0	0
T36	0	25	0	0
T37	0	31	0	0
T38	0	21	0	0
T39	0	24	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1643	0	0
T12	485034	47	0	0
T13	393091	0	0	0
T14	595340	0	0	0
T24	148498	0	0	0
T25	174668	0	0	0
T26	821468	0	0	0
T27	583962	0	0	0
T28	18603	0	0	0
T29	412987	0	0	0
T30	959815	0	0	0
T31	0	49	0	0
T32	0	9	0	0
T33	0	4	0	0
T34	0	20	0	0
T35	0	16	0	0
T36	0	26	0	0
T37	0	24	0	0
T38	0	14	0	0
T39	0	41	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1915	0	0
T12	485034	40	0	0
T13	393091	0	0	0
T14	595340	0	0	0
T24	148498	0	0	0
T25	174668	0	0	0
T26	821468	0	0	0
T27	583962	0	0	0
T28	18603	0	0	0
T29	412987	0	0	0
T30	959815	0	0	0
T31	0	38	0	0
T32	0	26	0	0
T33	0	13	0	0
T34	0	19	0	0
T35	0	10	0	0
T36	0	12	0	0
T37	0	26	0	0
T38	0	25	0	0
T39	0	39	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1688	0	0
T12	485034	41	0	0
T13	393091	0	0	0
T14	595340	0	0	0
T24	148498	0	0	0
T25	174668	0	0	0
T26	821468	0	0	0
T27	583962	0	0	0
T28	18603	0	0	0
T29	412987	0	0	0
T30	959815	0	0	0
T31	0	59	0	0
T32	0	19	0	0
T33	0	20	0	0
T34	0	19	0	0
T35	0	15	0	0
T36	0	22	0	0
T37	0	50	0	0
T38	0	13	0	0
T39	0	44	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1878	0	0
T12	485034	26	0	0
T13	393091	0	0	0
T14	595340	0	0	0
T24	148498	0	0	0
T25	174668	0	0	0
T26	821468	0	0	0
T27	583962	0	0	0
T28	18603	0	0	0
T29	412987	0	0	0
T30	959815	0	0	0
T31	0	29	0	0
T32	0	28	0	0
T33	0	4	0	0
T34	0	14	0	0
T35	0	26	0	0
T36	0	21	0	0
T37	0	24	0	0
T38	0	20	0	0
T39	0	39	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1500	0	0
T12	485034	27	0	0
T13	393091	0	0	0
T14	595340	0	0	0
T24	148498	0	0	0
T25	174668	0	0	0
T26	821468	0	0	0
T27	583962	0	0	0
T28	18603	0	0	0
T29	412987	0	0	0
T30	959815	0	0	0
T31	0	30	0	0
T32	0	20	0	0
T33	0	11	0	0
T34	0	14	0	0
T35	0	18	0	0
T36	0	16	0	0
T37	0	30	0	0
T38	0	18	0	0
T39	0	35	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1794	0	0
T12	485034	56	0	0
T13	393091	0	0	0
T14	595340	0	0	0
T24	148498	0	0	0
T25	174668	0	0	0
T26	821468	0	0	0
T27	583962	0	0	0
T28	18603	0	0	0
T29	412987	0	0	0
T30	959815	0	0	0
T31	0	35	0	0
T32	0	10	0	0
T33	0	22	0	0
T34	0	12	0	0
T35	0	21	0	0
T36	0	18	0	0
T37	0	42	0	0
T38	0	16	0	0
T39	0	52	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2026	0	0
T12	485034	33	0	0
T13	393091	0	0	0
T14	595340	0	0	0
T24	148498	0	0	0
T25	174668	0	0	0
T26	821468	0	0	0
T27	583962	0	0	0
T28	18603	0	0	0
T29	412987	0	0	0
T30	959815	0	0	0
T31	0	35	0	0
T32	0	11	0	0
T33	0	30	0	0
T34	0	22	0	0
T35	0	45	0	0
T36	0	23	0	0
T37	0	26	0	0
T38	0	25	0	0
T40	0	9	0	0