Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	5542	1			T1	20		T2	7		T4	20
testmodes[AdcCtrlTestmodeNormal]	4571	1			T2	13		T5	1		T6	4
testmodes[AdcCtrlTestmodeLowpower]	4718	1			T7	4		T11	17		T12	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	2920	1			T1	19		T2	2		T4	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1383	1			T2	4		T6	2		T7	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1110	1			T7	2		T35	1		T36	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1391	1			T2	5		T6	3		T7	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1721	1			T2	8		T6	1		T7	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1132	1			T7	2		T35	2		T31	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1108	1			T7	2		T35	1		T31	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1129	1			T7	1		T35	2		T36	4
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2239	1			T11	16		T48	14		T16	2