Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.71 99.07 96.67 100.00 100.00 98.83 98.33 91.07


Total tests in report: 920
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
79.44 79.44 98.73 98.73 87.24 87.24 89.10 89.10 78.38 78.38 97.90 97.90 92.15 92.15 12.55 12.55 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.1378290490
82.26 2.82 98.73 0.00 88.64 1.40 96.92 7.82 83.78 5.41 98.27 0.37 92.49 0.33 16.97 4.42 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2536707864
84.56 2.30 98.73 0.00 88.64 0.00 96.92 0.00 91.89 8.11 98.27 0.00 92.65 0.17 24.81 7.84 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all.1663545582
86.31 1.76 98.73 0.00 93.37 4.73 96.92 0.00 91.89 0.00 98.45 0.19 94.16 1.50 30.67 5.86 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.409508765
87.44 1.13 98.73 0.00 93.37 0.00 96.92 0.00 91.89 0.00 98.45 0.00 94.16 0.00 38.58 7.91 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_clock_gating.1487202119
88.35 0.91 98.73 0.00 93.37 0.00 96.92 0.00 91.89 0.00 98.45 0.00 94.16 0.00 44.95 6.36 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_clock_gating.2719844015
89.20 0.84 98.73 0.00 93.54 0.16 97.39 0.47 94.59 2.70 98.45 0.00 94.32 0.17 47.34 2.40 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.952765387
90.00 0.81 98.77 0.03 94.24 0.70 97.39 0.00 94.59 0.00 98.52 0.06 95.16 0.83 51.36 4.02 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_clock_gating.3577677031
90.64 0.64 98.77 0.00 94.24 0.00 97.39 0.00 94.59 0.00 98.52 0.00 95.16 0.00 55.83 4.47 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_clock_gating.72868894
91.21 0.56 98.77 0.00 94.24 0.00 97.39 0.00 94.59 0.00 98.52 0.00 95.16 0.00 59.77 3.94 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.303434543
91.75 0.54 98.77 0.00 94.24 0.00 97.39 0.00 97.30 2.70 98.52 0.00 95.16 0.00 60.87 1.10 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.703464080
92.20 0.45 98.77 0.00 94.24 0.00 97.39 0.00 100.00 2.70 98.52 0.00 95.16 0.00 61.34 0.47 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_stress_all.3670632923
92.64 0.43 98.80 0.03 94.36 0.12 99.76 2.37 100.00 0.00 98.58 0.06 95.49 0.33 61.47 0.12 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.997263102
93.05 0.42 98.92 0.12 94.40 0.04 99.76 0.00 100.00 0.00 98.64 0.06 95.49 0.00 64.16 2.70 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all.1269601697
93.42 0.37 98.92 0.00 94.40 0.00 99.76 0.00 100.00 0.00 98.64 0.00 95.99 0.50 66.23 2.07 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup.2987757108
93.74 0.32 98.92 0.00 94.40 0.00 99.76 0.00 100.00 0.00 98.64 0.00 95.99 0.00 68.46 2.22 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.241368997
94.03 0.29 98.92 0.00 95.64 1.24 99.76 0.00 100.00 0.00 98.70 0.06 96.33 0.33 68.88 0.42 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3846798520
94.32 0.28 98.92 0.00 95.64 0.00 99.76 0.00 100.00 0.00 98.70 0.00 96.49 0.17 70.70 1.82 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup.3328093125
94.57 0.25 98.98 0.06 95.88 0.25 99.76 0.00 100.00 0.00 98.83 0.12 97.83 1.34 70.70 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.615515641
94.81 0.24 98.98 0.00 95.88 0.00 99.76 0.00 100.00 0.00 98.83 0.00 97.83 0.00 72.40 1.70 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.3154507599
95.02 0.21 98.98 0.00 95.92 0.04 99.76 0.00 100.00 0.00 98.83 0.00 97.83 0.00 73.85 1.45 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt_fixed.512194329
95.22 0.20 98.98 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.83 0.00 98.16 0.33 74.89 1.05 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_both.3642778114
95.40 0.18 98.98 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.83 0.00 98.16 0.00 76.17 1.27 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_clock_gating.1378970134
95.55 0.15 98.98 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.83 0.00 98.16 0.00 77.21 1.05 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_clock_gating.682454852
95.69 0.14 98.98 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.83 0.00 98.16 0.00 78.19 0.97 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_both.1785414152
95.82 0.13 98.98 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.83 0.00 98.16 0.00 79.09 0.90 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.3476176771
95.95 0.13 98.98 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.83 0.00 98.16 0.00 79.99 0.90 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all.3636758211
96.06 0.11 98.98 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.83 0.00 98.16 0.00 80.78 0.80 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_both.2274865039
96.17 0.10 98.98 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.83 0.00 98.16 0.00 81.51 0.72 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt.1829420787
96.27 0.10 98.98 0.00 96.13 0.21 99.76 0.00 100.00 0.00 98.83 0.00 98.16 0.00 82.01 0.50 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1924313857
96.36 0.09 98.98 0.00 96.13 0.00 99.76 0.00 100.00 0.00 98.83 0.00 98.16 0.00 82.63 0.62 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_both.4122577323
96.43 0.08 98.98 0.00 96.13 0.00 99.76 0.00 100.00 0.00 98.83 0.00 98.33 0.17 83.00 0.37 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_wakeup.4101698689
96.51 0.07 98.98 0.00 96.13 0.00 99.76 0.00 100.00 0.00 98.83 0.00 98.33 0.00 83.53 0.52 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_both.2586007828
96.58 0.07 98.98 0.00 96.13 0.00 99.76 0.00 100.00 0.00 98.83 0.00 98.33 0.00 84.00 0.47 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_both.1859203191
96.64 0.07 98.98 0.00 96.42 0.29 99.76 0.00 100.00 0.00 98.83 0.00 98.33 0.00 84.18 0.17 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3217736708
96.71 0.06 99.07 0.09 96.54 0.12 100.00 0.24 100.00 0.00 98.83 0.00 98.33 0.00 84.18 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.2116645585
96.77 0.06 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 84.63 0.45 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_clock_gating.3221243188
96.83 0.06 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 85.05 0.42 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt.2699770482
96.89 0.06 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 85.45 0.40 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_clock_gating.864484203
96.94 0.05 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 85.82 0.37 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all.1141494102
97.00 0.05 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 86.20 0.37 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_both.1644464398
97.05 0.05 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 86.55 0.35 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_interrupt.2101634992
97.09 0.04 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 86.85 0.30 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_clock_gating.3058192455
97.13 0.04 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 87.12 0.27 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt.1946990020
97.17 0.04 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 87.40 0.27 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_clock_gating.2193784551
97.20 0.04 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 87.65 0.25 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_fsm_reset.3909795814
97.23 0.03 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 87.87 0.22 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_both.1487397534
97.26 0.03 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 88.07 0.20 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_stress_all.106611372
97.29 0.03 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 88.27 0.20 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled.2178430768
97.32 0.02 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 88.45 0.17 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt.2000436979
97.34 0.02 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 88.59 0.15 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_stress_all.44612849
97.36 0.02 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 88.72 0.12 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup.2019048931
97.37 0.02 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 88.84 0.12 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_both.415788622
97.39 0.02 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 88.97 0.12 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_polled.4030193693
97.41 0.02 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.09 0.12 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_both.312043151
97.43 0.02 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.22 0.12 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_both.618917119
97.44 0.01 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.32 0.10 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all.3710680075
97.46 0.01 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.42 0.10 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_wakeup.3478358025
97.47 0.01 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.52 0.10 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_wakeup.3043757329
97.48 0.01 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.62 0.10 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.1750015786
97.50 0.01 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.72 0.10 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_polled.558185093
97.51 0.01 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.82 0.10 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_clock_gating.3003859656
97.53 0.01 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.92 0.10 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_wakeup.1054588647
97.54 0.01 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.02 0.10 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_polled.2424045619
97.56 0.01 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.12 0.10 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt.2777094388
97.57 0.01 99.07 0.00 96.58 0.04 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.17 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3852763299
97.58 0.01 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.24 0.07 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_both.3890937391
97.59 0.01 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.32 0.07 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_clock_gating.3108085535
97.60 0.01 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.39 0.07 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_interrupt.3017186793
97.61 0.01 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.44 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3270885670
97.62 0.01 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.49 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup.1250095668
97.62 0.01 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.54 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_clock_gating.3798966841
97.63 0.01 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.59 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_polled.1081220199
97.64 0.01 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.64 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_fsm_reset.967835173
97.64 0.01 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.69 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_fsm_reset.125071448
97.65 0.01 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.74 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_stress_all.1925404776
97.66 0.01 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.79 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_both.742392763
97.66 0.01 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.84 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.1715806343
97.67 0.01 99.07 0.00 96.62 0.04 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.84 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2152585981
97.68 0.01 99.07 0.00 96.67 0.04 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.84 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_smoke.2816378922
97.68 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.87 0.02 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt.737168717
97.68 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.89 0.02 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup.4084987071
97.69 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.92 0.02 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_clock_gating.3476410647
97.69 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.94 0.02 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_wakeup.952651022
97.69 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.97 0.02 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_interrupt.705380444
97.70 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.99 0.02 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_wakeup.1215587109
97.70 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 91.02 0.02 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_both.3011130701
97.71 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 91.04 0.02 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_stress_all.789684856
97.71 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 91.07 0.02 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_clock_gating.1171890932

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.4244380159
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1942169226
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1711615825
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.36374112
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2416087176
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.522575188
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1576651222
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1371459413
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.555252049
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2652168148
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2699523584
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2055697372
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.3907790679
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3724290768
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1793716423
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3659268370
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2722650266
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3339922213
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.1022089055
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3314957602
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2668603886
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2997655230
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.183214553
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.553091635
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.3123642134
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2297559847
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.4253423287
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.4273172802
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1838987348
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3426239297
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.369990063
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3162428135
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3274767528
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3382813367
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.43327060
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3518957824
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.3135041561
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3412485909
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3006241719
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3105236034
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.140098602
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.2763306590
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1670371377
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.4274279218
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2389379311
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1921649682
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1449791039
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.3072119467
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2894609873
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3682738406
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1201730479
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.126183242
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2611411807
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.226532548
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2226539164
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.258056087
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3623454848
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2010508402
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1070642125
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.3324751432
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1431065538
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1568059803
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.341868478
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3959216478
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.2961017246
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2628006576
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1168256537
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2631051444
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3071827944
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3921351664
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.2064493461
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.108682414
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2582429663
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.897303236
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.883944470
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.170036378
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2310272347
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1174497229
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.2994365181
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1085783492
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2782182350
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2707816189
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.1751103343
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.4124237743
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.3640403309
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.1899419611
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.2346749502
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.3041318448
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.4184903708
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.39919857
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.3950330480
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.2162109543
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3273091181
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.358793042
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3694626729
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3650760698
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1360116194
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.396490834
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3050580485
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2268212167
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/30.adc_ctrl_intr_test.478545234
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/31.adc_ctrl_intr_test.848255856
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/32.adc_ctrl_intr_test.1307049133
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/33.adc_ctrl_intr_test.1746768884
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/34.adc_ctrl_intr_test.4266090063
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/35.adc_ctrl_intr_test.853032170
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/36.adc_ctrl_intr_test.2988939192
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/37.adc_ctrl_intr_test.458847425
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/38.adc_ctrl_intr_test.2901288463
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/39.adc_ctrl_intr_test.562677956
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2338776485
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1190956088
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Total test records in report: 920
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_smoke.2816378922 Aug 23 04:14:35 AM UTC 24 Aug 23 04:14:40 AM UTC 24 5670729375 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_poweron_counter.708164193 Aug 23 04:14:59 AM UTC 24 Aug 23 04:15:02 AM UTC 24 5585211655 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.997263102 Aug 23 04:15:08 AM UTC 24 Aug 23 04:15:14 AM UTC 24 8004971936 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.2116645585 Aug 23 04:15:15 AM UTC 24 Aug 23 04:15:18 AM UTC 24 343371717 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_smoke.3917357763 Aug 23 04:15:15 AM UTC 24 Aug 23 04:15:21 AM UTC 24 5845757218 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt_fixed.512194329 Aug 23 04:14:44 AM UTC 24 Aug 23 04:15:37 AM UTC 24 161485701758 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_poweron_counter.1898246196 Aug 23 04:15:42 AM UTC 24 Aug 23 04:15:49 AM UTC 24 2736583423 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.1378290490 Aug 23 04:15:05 AM UTC 24 Aug 23 04:15:59 AM UTC 24 409915097080 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.4198014258 Aug 23 04:15:54 AM UTC 24 Aug 23 04:16:01 AM UTC 24 4015078848 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_alert_test.478682757 Aug 23 04:16:02 AM UTC 24 Aug 23 04:16:04 AM UTC 24 295889897 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_smoke.4088259483 Aug 23 04:16:03 AM UTC 24 Aug 23 04:16:11 AM UTC 24 5603279498 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_sec_cm.2270342744 Aug 23 04:16:01 AM UTC 24 Aug 23 04:16:12 AM UTC 24 7923867371 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_clock_gating.3577677031 Aug 23 04:14:55 AM UTC 24 Aug 23 04:16:24 AM UTC 24 163241374972 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_lowpower_counter.2989088608 Aug 23 04:15:02 AM UTC 24 Aug 23 04:16:34 AM UTC 24 38939303800 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup_fixed.458900002 Aug 23 04:14:49 AM UTC 24 Aug 23 04:16:45 AM UTC 24 205027099326 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_poweron_counter.1919735157 Aug 23 04:16:46 AM UTC 24 Aug 23 04:16:50 AM UTC 24 5057280409 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup.2019048931 Aug 23 04:15:23 AM UTC 24 Aug 23 04:16:54 AM UTC 24 171483340519 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_lowpower_counter.1182724517 Aug 23 04:15:45 AM UTC 24 Aug 23 04:16:55 AM UTC 24 33610929226 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1614507651 Aug 23 04:16:56 AM UTC 24 Aug 23 04:17:01 AM UTC 24 1590142388 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.3426577546 Aug 23 04:15:38 AM UTC 24 Aug 23 04:17:07 AM UTC 24 162447946121 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt.3354804586 Aug 23 04:15:21 AM UTC 24 Aug 23 04:17:12 AM UTC 24 168201877727 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_alert_test.1554775068 Aug 23 04:17:13 AM UTC 24 Aug 23 04:17:15 AM UTC 24 462076512 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_smoke.347642060 Aug 23 04:17:16 AM UTC 24 Aug 23 04:17:19 AM UTC 24 5639243856 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_sec_cm.1297095781 Aug 23 04:17:08 AM UTC 24 Aug 23 04:17:27 AM UTC 24 8204950363 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup_fixed.3885632853 Aug 23 04:15:27 AM UTC 24 Aug 23 04:17:31 AM UTC 24 607948482128 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled.698997148 Aug 23 04:16:04 AM UTC 24 Aug 23 04:17:37 AM UTC 24 166227230811 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt.599158625 Aug 23 04:14:42 AM UTC 24 Aug 23 04:17:52 AM UTC 24 325317163643 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_poweron_counter.2745798515 Aug 23 04:17:52 AM UTC 24 Aug 23 04:17:57 AM UTC 24 2875106571 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.409508765 Aug 23 04:16:26 AM UTC 24 Aug 23 04:17:59 AM UTC 24 326586385044 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_lowpower_counter.483111153 Aug 23 04:16:51 AM UTC 24 Aug 23 04:18:17 AM UTC 24 38341649261 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2536707864 Aug 23 04:18:18 AM UTC 24 Aug 23 04:18:39 AM UTC 24 65671143386 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup.3700998844 Aug 23 04:17:35 AM UTC 24 Aug 23 04:18:41 AM UTC 24 362474218006 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_alert_test.2405664704 Aug 23 04:18:42 AM UTC 24 Aug 23 04:18:45 AM UTC 24 481799195 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_sec_cm.2048154416 Aug 23 04:18:40 AM UTC 24 Aug 23 04:18:50 AM UTC 24 8295051317 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_smoke.1027131417 Aug 23 04:18:46 AM UTC 24 Aug 23 04:19:02 AM UTC 24 5868083957 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_lowpower_counter.1730853198 Aug 23 04:17:58 AM UTC 24 Aug 23 04:19:08 AM UTC 24 31613399853 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt.2609036962 Aug 23 04:16:12 AM UTC 24 Aug 23 04:19:13 AM UTC 24 163286208119 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3876673453 Aug 23 04:16:13 AM UTC 24 Aug 23 04:19:16 AM UTC 24 167074880316 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all.1652410353 Aug 23 04:15:05 AM UTC 24 Aug 23 04:19:20 AM UTC 24 218771149075 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup.3328093125 Aug 23 04:14:49 AM UTC 24 Aug 23 04:19:38 AM UTC 24 560605322280 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled_fixed.289345394 Aug 23 04:17:27 AM UTC 24 Aug 23 04:19:42 AM UTC 24 325570186187 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup_fixed.1751118476 Aug 23 04:19:20 AM UTC 24 Aug 23 04:19:45 AM UTC 24 196094108040 ps
T357 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_poweron_counter.2087781592 Aug 23 04:19:45 AM UTC 24 Aug 23 04:19:49 AM UTC 24 3658531507 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled.2660793292 Aug 23 04:17:20 AM UTC 24 Aug 23 04:20:12 AM UTC 24 163718672290 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt_fixed.881573465 Aug 23 04:15:22 AM UTC 24 Aug 23 04:20:14 AM UTC 24 489289690971 ps
T358 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_lowpower_counter.2778517371 Aug 23 04:19:50 AM UTC 24 Aug 23 04:20:46 AM UTC 24 28041480229 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled.2473968521 Aug 23 04:14:37 AM UTC 24 Aug 23 04:20:47 AM UTC 24 321771682237 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3163230483 Aug 23 04:17:33 AM UTC 24 Aug 23 04:20:47 AM UTC 24 491271597944 ps
T359 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_alert_test.1339545724 Aug 23 04:20:48 AM UTC 24 Aug 23 04:20:49 AM UTC 24 540701207 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt_fixed.529958140 Aug 23 04:19:13 AM UTC 24 Aug 23 04:20:51 AM UTC 24 165078777086 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_sec_cm.1883390910 Aug 23 04:20:48 AM UTC 24 Aug 23 04:20:58 AM UTC 24 4089793213 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.926050863 Aug 23 04:20:15 AM UTC 24 Aug 23 04:20:59 AM UTC 24 13878175271 ps
T360 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_smoke.4147987067 Aug 23 04:20:50 AM UTC 24 Aug 23 04:21:02 AM UTC 24 6193293680 ps
T361 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled_fixed.3392763633 Aug 23 04:15:19 AM UTC 24 Aug 23 04:21:21 AM UTC 24 329015574884 ps
T131 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup_fixed.3726057246 Aug 23 04:16:24 AM UTC 24 Aug 23 04:21:27 AM UTC 24 608802371188 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_both.4206901615 Aug 23 04:15:38 AM UTC 24 Aug 23 04:21:47 AM UTC 24 179657988187 ps
T132 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_both.984179818 Aug 23 04:19:43 AM UTC 24 Aug 23 04:21:53 AM UTC 24 341734773911 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_clock_gating.2719844015 Aug 23 04:19:39 AM UTC 24 Aug 23 04:22:08 AM UTC 24 501682861644 ps
T362 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_poweron_counter.3582232982 Aug 23 04:22:09 AM UTC 24 Aug 23 04:22:14 AM UTC 24 5082616392 ps
T363 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled_fixed.3208775323 Aug 23 04:16:12 AM UTC 24 Aug 23 04:22:18 AM UTC 24 166131417359 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt.1503043053 Aug 23 04:19:09 AM UTC 24 Aug 23 04:22:21 AM UTC 24 161722804419 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.703464080 Aug 23 04:22:22 AM UTC 24 Aug 23 04:22:30 AM UTC 24 5896093993 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt.3024282153 Aug 23 04:17:30 AM UTC 24 Aug 23 04:23:14 AM UTC 24 331878982687 ps
T364 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_alert_test.316794545 Aug 23 04:23:15 AM UTC 24 Aug 23 04:23:17 AM UTC 24 462966554 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.1750015786 Aug 23 04:18:00 AM UTC 24 Aug 23 04:23:22 AM UTC 24 96645724227 ps
T365 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_smoke.1282405399 Aug 23 04:23:18 AM UTC 24 Aug 23 04:23:23 AM UTC 24 6046881198 ps
T366 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_lowpower_counter.2262208419 Aug 23 04:22:15 AM UTC 24 Aug 23 04:23:23 AM UTC 24 31942905513 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_clock_gating.179496905 Aug 23 04:17:42 AM UTC 24 Aug 23 04:23:24 AM UTC 24 165633665122 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3964646015 Aug 23 04:21:02 AM UTC 24 Aug 23 04:23:44 AM UTC 24 330362692674 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_fsm_reset.1986097650 Aug 23 04:16:56 AM UTC 24 Aug 23 04:23:56 AM UTC 24 77470544628 ps
T367 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup_fixed.572442528 Aug 23 04:17:38 AM UTC 24 Aug 23 04:24:02 AM UTC 24 585749401860 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled.2418624588 Aug 23 04:20:52 AM UTC 24 Aug 23 04:24:17 AM UTC 24 340275242629 ps
T368 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled_fixed.2679895138 Aug 23 04:19:03 AM UTC 24 Aug 23 04:24:21 AM UTC 24 489572504397 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.1544939036 Aug 23 04:17:47 AM UTC 24 Aug 23 04:24:30 AM UTC 24 184176184317 ps
T369 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_poweron_counter.3373162533 Aug 23 04:24:21 AM UTC 24 Aug 23 04:24:30 AM UTC 24 2997395283 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_both.1785414152 Aug 23 04:14:58 AM UTC 24 Aug 23 04:24:55 AM UTC 24 524797463355 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt_fixed.765938104 Aug 23 04:23:25 AM UTC 24 Aug 23 04:24:57 AM UTC 24 159889903372 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3604971945 Aug 23 04:24:55 AM UTC 24 Aug 23 04:25:00 AM UTC 24 1620474136 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_alert_test.3020158784 Aug 23 04:25:01 AM UTC 24 Aug 23 04:25:03 AM UTC 24 340942777 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_fsm_reset.3909795814 Aug 23 04:15:04 AM UTC 24 Aug 23 04:25:03 AM UTC 24 116069176588 ps
T371 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup_fixed.414587276 Aug 23 04:21:27 AM UTC 24 Aug 23 04:25:04 AM UTC 24 400246923550 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_fsm_reset.192993494 Aug 23 04:15:49 AM UTC 24 Aug 23 04:25:04 AM UTC 24 108309185254 ps
T372 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_lowpower_counter.3377458638 Aug 23 04:24:31 AM UTC 24 Aug 23 04:25:06 AM UTC 24 30497127033 ps
T373 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_smoke.2880078214 Aug 23 04:25:04 AM UTC 24 Aug 23 04:25:12 AM UTC 24 5749727418 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.241368997 Aug 23 04:23:24 AM UTC 24 Aug 23 04:25:23 AM UTC 24 330486106723 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_clock_gating.682454852 Aug 23 04:24:03 AM UTC 24 Aug 23 04:25:56 AM UTC 24 520359123391 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup.3531286539 Aug 23 04:19:17 AM UTC 24 Aug 23 04:26:09 AM UTC 24 193849755668 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled.2178430768 Aug 23 04:23:23 AM UTC 24 Aug 23 04:26:11 AM UTC 24 325629488785 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled.3835324523 Aug 23 04:15:17 AM UTC 24 Aug 23 04:26:13 AM UTC 24 330689242753 ps
T374 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_poweron_counter.1597898727 Aug 23 04:26:11 AM UTC 24 Aug 23 04:26:16 AM UTC 24 4576136026 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup.2987757108 Aug 23 04:21:21 AM UTC 24 Aug 23 04:26:33 AM UTC 24 546058957280 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2387538783 Aug 23 04:25:07 AM UTC 24 Aug 23 04:26:37 AM UTC 24 158984250664 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt.3834229426 Aug 23 04:21:00 AM UTC 24 Aug 23 04:26:38 AM UTC 24 161999846577 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled_fixed.2232833610 Aug 23 04:20:59 AM UTC 24 Aug 23 04:26:38 AM UTC 24 161893021907 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_alert_test.1793512933 Aug 23 04:26:38 AM UTC 24 Aug 23 04:26:41 AM UTC 24 516202202 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3027953401 Aug 23 04:26:34 AM UTC 24 Aug 23 04:26:43 AM UTC 24 24708015270 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_smoke.1004180282 Aug 23 04:26:40 AM UTC 24 Aug 23 04:26:54 AM UTC 24 5737545494 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_lowpower_counter.756685737 Aug 23 04:26:13 AM UTC 24 Aug 23 04:27:33 AM UTC 24 36147397619 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_clock_gating.1487202119 Aug 23 04:21:47 AM UTC 24 Aug 23 04:27:46 AM UTC 24 532396974957 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_both.1405871337 Aug 23 04:21:54 AM UTC 24 Aug 23 04:27:51 AM UTC 24 162089426438 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup.2967034854 Aug 23 04:16:24 AM UTC 24 Aug 23 04:27:53 AM UTC 24 342388588608 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.3476176771 Aug 23 04:15:59 AM UTC 24 Aug 23 04:27:59 AM UTC 24 325102260592 ps
T130 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all.287858537 Aug 23 04:26:37 AM UTC 24 Aug 23 04:28:00 AM UTC 24 160897790887 ps
T375 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup_fixed.467776938 Aug 23 04:23:57 AM UTC 24 Aug 23 04:28:02 AM UTC 24 392266730647 ps
T376 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_poweron_counter.382567681 Aug 23 04:28:00 AM UTC 24 Aug 23 04:28:04 AM UTC 24 4562842042 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled.1765443719 Aug 23 04:18:51 AM UTC 24 Aug 23 04:28:37 AM UTC 24 324665696302 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_both.622765437 Aug 23 04:28:00 AM UTC 24 Aug 23 04:28:41 AM UTC 24 167674137268 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1924313857 Aug 23 04:28:37 AM UTC 24 Aug 23 04:28:44 AM UTC 24 7322318536 ps
T377 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_alert_test.1505342314 Aug 23 04:28:44 AM UTC 24 Aug 23 04:28:46 AM UTC 24 331618088 ps
T378 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_smoke.1645640074 Aug 23 04:28:46 AM UTC 24 Aug 23 04:28:50 AM UTC 24 5561360165 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_both.2586007828 Aug 23 04:26:10 AM UTC 24 Aug 23 04:28:55 AM UTC 24 341690517019 ps
T379 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled_fixed.4002575024 Aug 23 04:23:24 AM UTC 24 Aug 23 04:29:04 AM UTC 24 491532729840 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_fsm_reset.1787422110 Aug 23 04:20:13 AM UTC 24 Aug 23 04:29:06 AM UTC 24 102328817023 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_fsm_reset.1507067644 Aug 23 04:22:20 AM UTC 24 Aug 23 04:29:16 AM UTC 24 71029883179 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt.44790344 Aug 23 04:25:05 AM UTC 24 Aug 23 04:29:16 AM UTC 24 503735836633 ps
T380 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled_fixed.1712006514 Aug 23 04:25:05 AM UTC 24 Aug 23 04:29:17 AM UTC 24 484246896321 ps
T381 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_lowpower_counter.438247827 Aug 23 04:28:02 AM UTC 24 Aug 23 04:29:29 AM UTC 24 37520410472 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup.1011737809 Aug 23 04:25:13 AM UTC 24 Aug 23 04:30:13 AM UTC 24 527178397293 ps
T382 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_poweron_counter.2965124985 Aug 23 04:30:14 AM UTC 24 Aug 23 04:30:18 AM UTC 24 3847377778 ps
T383 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt_fixed.3279485222 Aug 23 04:27:34 AM UTC 24 Aug 23 04:30:34 AM UTC 24 165092588259 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all.1678062977 Aug 23 04:17:02 AM UTC 24 Aug 23 04:30:35 AM UTC 24 283255574747 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_fsm_reset.2168999796 Aug 23 04:26:16 AM UTC 24 Aug 23 04:30:45 AM UTC 24 86071715670 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.1715806343 Aug 23 04:30:36 AM UTC 24 Aug 23 04:30:46 AM UTC 24 6872850564 ps
T384 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_alert_test.3083706916 Aug 23 04:30:47 AM UTC 24 Aug 23 04:30:49 AM UTC 24 325900373 ps
T385 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_smoke.3807817605 Aug 23 04:30:49 AM UTC 24 Aug 23 04:31:03 AM UTC 24 5660484331 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_clock_gating.3221243188 Aug 23 04:27:54 AM UTC 24 Aug 23 04:31:19 AM UTC 24 328011119435 ps
T386 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_lowpower_counter.3633732454 Aug 23 04:30:18 AM UTC 24 Aug 23 04:31:25 AM UTC 24 32508407521 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all.1663545582 Aug 23 04:20:47 AM UTC 24 Aug 23 04:31:51 AM UTC 24 624394955264 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled_fixed.1341544003 Aug 23 04:31:20 AM UTC 24 Aug 23 04:31:57 AM UTC 24 161447476422 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all.552924279 Aug 23 04:22:31 AM UTC 24 Aug 23 04:31:59 AM UTC 24 321311785596 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled.3327506330 Aug 23 04:31:04 AM UTC 24 Aug 23 04:32:03 AM UTC 24 320178011845 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled_fixed.1033427651 Aug 23 04:14:41 AM UTC 24 Aug 23 04:32:07 AM UTC 24 487496572866 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_both.3712670206 Aug 23 04:29:30 AM UTC 24 Aug 23 04:32:23 AM UTC 24 163212653484 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_poweron_counter.1856881404 Aug 23 04:32:24 AM UTC 24 Aug 23 04:32:37 AM UTC 24 5240216036 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup_fixed.14821752 Aug 23 04:25:23 AM UTC 24 Aug 23 04:32:39 AM UTC 24 394301897189 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_fsm_reset.1188426725 Aug 23 04:24:31 AM UTC 24 Aug 23 04:32:53 AM UTC 24 96728322283 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_fsm_reset.1419622659 Aug 23 04:28:05 AM UTC 24 Aug 23 04:33:00 AM UTC 24 109047737187 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2293408440 Aug 23 04:32:54 AM UTC 24 Aug 23 04:33:06 AM UTC 24 19295088396 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_alert_test.3569434599 Aug 23 04:33:07 AM UTC 24 Aug 23 04:33:10 AM UTC 24 480453282 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1551817977 Aug 23 04:29:17 AM UTC 24 Aug 23 04:33:16 AM UTC 24 417354906896 ps
T387 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_smoke.3279600955 Aug 23 04:33:10 AM UTC 24 Aug 23 04:33:26 AM UTC 24 5998823511 ps
T388 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt_fixed.1193342058 Aug 23 04:31:52 AM UTC 24 Aug 23 04:33:34 AM UTC 24 169531679946 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.3154507599 Aug 23 04:31:58 AM UTC 24 Aug 23 04:33:46 AM UTC 24 557609175038 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_both.1664547729 Aug 23 04:32:08 AM UTC 24 Aug 23 04:33:46 AM UTC 24 165868876657 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.539857125 Aug 23 04:34:34 AM UTC 24 Aug 23 04:34:47 AM UTC 24 4363575413 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.303434543 Aug 23 04:16:35 AM UTC 24 Aug 23 04:33:48 AM UTC 24 506245536667 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all.1808597336 Aug 23 04:30:46 AM UTC 24 Aug 23 04:34:01 AM UTC 24 369421530656 ps
T389 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_lowpower_counter.3992562475 Aug 23 04:32:38 AM UTC 24 Aug 23 04:34:02 AM UTC 24 40370240822 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.607230131 Aug 23 04:32:04 AM UTC 24 Aug 23 04:34:05 AM UTC 24 164156680891 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_poweron_counter.1918669191 Aug 23 04:34:06 AM UTC 24 Aug 23 04:34:16 AM UTC 24 4040686358 ps
T391 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_lowpower_counter.2591775073 Aug 23 04:34:17 AM UTC 24 Aug 23 04:34:32 AM UTC 24 28709471004 ps
T392 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all.2964399514 Aug 23 04:33:01 AM UTC 24 Aug 23 04:34:33 AM UTC 24 233660720463 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled.2163569618 Aug 23 04:28:50 AM UTC 24 Aug 23 04:34:41 AM UTC 24 157029203598 ps
T393 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1410458717 Aug 23 04:33:48 AM UTC 24 Aug 23 04:34:45 AM UTC 24 406489151937 ps
T394 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_alert_test.3904838769 Aug 23 04:34:45 AM UTC 24 Aug 23 04:34:47 AM UTC 24 404547938 ps
T395 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_smoke.402627979 Aug 23 04:34:47 AM UTC 24 Aug 23 04:34:51 AM UTC 24 6020532585 ps
T396 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1239468217 Aug 23 04:27:51 AM UTC 24 Aug 23 04:34:56 AM UTC 24 193887549360 ps
T397 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt_fixed.4208004636 Aug 23 04:33:46 AM UTC 24 Aug 23 04:35:05 AM UTC 24 319827634930 ps
T398 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.463292364 Aug 23 04:30:34 AM UTC 24 Aug 23 04:35:13 AM UTC 24 71404072362 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup.2727201540 Aug 23 04:33:47 AM UTC 24 Aug 23 04:35:20 AM UTC 24 168394568453 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_clock_gating.2987494121 Aug 23 04:29:18 AM UTC 24 Aug 23 04:36:42 AM UTC 24 386884837698 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt.2830578516 Aug 23 04:33:34 AM UTC 24 Aug 23 04:36:54 AM UTC 24 160485658769 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_both.1312729826 Aug 23 04:34:04 AM UTC 24 Aug 23 04:37:11 AM UTC 24 161387583391 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup.2289141533 Aug 23 04:35:14 AM UTC 24 Aug 23 04:37:15 AM UTC 24 359905546127 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all.376721772 Aug 23 04:24:58 AM UTC 24 Aug 23 04:37:17 AM UTC 24 242209990194 ps
T399 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_poweron_counter.2513238593 Aug 23 04:37:12 AM UTC 24 Aug 23 04:37:24 AM UTC 24 5280365427 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1047131898 Aug 23 04:37:25 AM UTC 24 Aug 23 04:37:30 AM UTC 24 792620956 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled.3310154649 Aug 23 04:33:17 AM UTC 24 Aug 23 04:37:45 AM UTC 24 330079645160 ps
T400 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_alert_test.1304133237 Aug 23 04:37:45 AM UTC 24 Aug 23 04:37:47 AM UTC 24 329349096 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_clock_gating.72868894 Aug 23 04:34:02 AM UTC 24 Aug 23 04:37:51 AM UTC 24 541305834358 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled.765551872 Aug 23 04:25:04 AM UTC 24 Aug 23 04:37:52 AM UTC 24 332154534384 ps
T401 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3515281649 Aug 23 04:35:20 AM UTC 24 Aug 23 04:37:56 AM UTC 24 600171684346 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_clock_gating.1540834581 Aug 23 04:25:57 AM UTC 24 Aug 23 04:37:59 AM UTC 24 340622496764 ps
T402 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_smoke.4165945650 Aug 23 04:37:48 AM UTC 24 Aug 23 04:38:01 AM UTC 24 5840502351 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_lowpower_counter.3194813429 Aug 23 04:37:16 AM UTC 24 Aug 23 04:38:03 AM UTC 24 42794743765 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_fsm_reset.4255527742 Aug 23 04:34:34 AM UTC 24 Aug 23 04:38:40 AM UTC 24 71920770361 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt.528623214 Aug 23 04:26:55 AM UTC 24 Aug 23 04:39:06 AM UTC 24 329974545268 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled_fixed.3715732576 Aug 23 04:37:53 AM UTC 24 Aug 23 04:39:25 AM UTC 24 160523292058 ps
T405 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_poweron_counter.3888338098 Aug 23 04:39:26 AM UTC 24 Aug 23 04:39:36 AM UTC 24 4587255800 ps
T406 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_lowpower_counter.3690154824 Aug 23 04:39:37 AM UTC 24 Aug 23 04:39:56 AM UTC 24 34734668314 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup.1291519836 Aug 23 04:27:47 AM UTC 24 Aug 23 04:40:08 AM UTC 24 373405861552 ps
T407 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled_fixed.3289539677 Aug 23 04:34:52 AM UTC 24 Aug 23 04:40:15 AM UTC 24 167569531381 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_clock_gating.1743187737 Aug 23 04:38:41 AM UTC 24 Aug 23 04:40:18 AM UTC 24 173924307651 ps
T408 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_alert_test.521292995 Aug 23 04:40:19 AM UTC 24 Aug 23 04:40:22 AM UTC 24 382325754 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3279064251 Aug 23 04:40:09 AM UTC 24 Aug 23 04:40:24 AM UTC 24 2691489487 ps
T410 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_smoke.2672214535 Aug 23 04:40:22 AM UTC 24 Aug 23 04:40:26 AM UTC 24 6048558119 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt_fixed.713068525 Aug 23 04:29:07 AM UTC 24 Aug 23 04:40:36 AM UTC 24 331170982382 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all.1445031215 Aug 23 04:37:31 AM UTC 24 Aug 23 04:41:11 AM UTC 24 369271866206 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup.182760893 Aug 23 04:23:45 AM UTC 24 Aug 23 04:41:17 AM UTC 24 524001612673 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1860826277 Aug 23 04:35:06 AM UTC 24 Aug 23 04:41:26 AM UTC 24 168626849175 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_both.3893779193 Aug 23 04:36:55 AM UTC 24 Aug 23 04:41:28 AM UTC 24 498339331177 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_clock_gating.2068802705 Aug 23 04:41:29 AM UTC 24 Aug 23 04:42:05 AM UTC 24 166897972554 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all.1813269149 Aug 23 04:28:42 AM UTC 24 Aug 23 04:42:27 AM UTC 24 391916720328 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_poweron_counter.928312665 Aug 23 04:42:28 AM UTC 24 Aug 23 04:42:32 AM UTC 24 4106368122 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt_fixed.3932598062 Aug 23 04:41:12 AM UTC 24 Aug 23 04:42:45 AM UTC 24 166310094605 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_lowpower_counter.2576084307 Aug 23 04:42:33 AM UTC 24 Aug 23 04:42:52 AM UTC 24 30411317480 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup.501347010 Aug 23 04:29:17 AM UTC 24 Aug 23 04:42:55 AM UTC 24 399093711013 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.2568285578 Aug 23 04:42:53 AM UTC 24 Aug 23 04:43:01 AM UTC 24 10976453125 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_alert_test.295825474 Aug 23 04:43:01 AM UTC 24 Aug 23 04:43:03 AM UTC 24 366055626 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled.279927411 Aug 23 04:40:25 AM UTC 24 Aug 23 04:43:12 AM UTC 24 164755544384 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_both.3299742572 Aug 23 04:24:18 AM UTC 24 Aug 23 04:43:15 AM UTC 24 527541976737 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_smoke.2652388622 Aug 23 04:43:04 AM UTC 24 Aug 23 04:43:17 AM UTC 24 5857857601 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt.737168717 Aug 23 04:31:25 AM UTC 24 Aug 23 04:44:00 AM UTC 24 331872389620 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_fsm_reset.592918868 Aug 23 04:32:40 AM UTC 24 Aug 23 04:44:19 AM UTC 24 138870439353 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_fsm_reset.2263324582 Aug 23 04:37:18 AM UTC 24 Aug 23 04:44:29 AM UTC 24 84602515578 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled_fixed.4039970299 Aug 23 04:26:44 AM UTC 24 Aug 23 04:44:30 AM UTC 24 493051888497 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled_fixed.4115046701 Aug 23 04:40:27 AM UTC 24 Aug 23 04:44:46 AM UTC 24 497066333181 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled.1467922202 Aug 23 04:26:42 AM UTC 24 Aug 23 04:44:48 AM UTC 24 499205912060 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_poweron_counter.3049926730 Aug 23 04:44:49 AM UTC 24 Aug 23 04:44:51 AM UTC 24 4518786067 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup_fixed.796396811 Aug 23 04:44:30 AM UTC 24 Aug 23 04:44:57 AM UTC 24 208129994809 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_both.1160636458 Aug 23 04:39:07 AM UTC 24 Aug 23 04:44:59 AM UTC 24 329802024645 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup_fixed.156381396 Aug 23 04:38:03 AM UTC 24 Aug 23 04:45:00 AM UTC 24 201828949845 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled_fixed.4104418030 Aug 23 04:28:56 AM UTC 24 Aug 23 04:45:07 AM UTC 24 483132720162 ps
T425 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_alert_test.386088287 Aug 23 04:45:08 AM UTC 24 Aug 23 04:45:10 AM UTC 24 423526722 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_lowpower_counter.407283377 Aug 23 04:44:52 AM UTC 24 Aug 23 04:45:10 AM UTC 24 30095666538 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.4248635550 Aug 23 04:45:00 AM UTC 24 Aug 23 04:45:17 AM UTC 24 7378614125 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_smoke.3034932448 Aug 23 04:45:11 AM UTC 24 Aug 23 04:45:26 AM UTC 24 5879563905 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all.1269601697 Aug 23 04:18:21 AM UTC 24 Aug 23 04:45:33 AM UTC 24 605600267115 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2816088692 Aug 23 04:44:00 AM UTC 24 Aug 23 04:45:46 AM UTC 24 325692020095 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt.3163908998 Aug 23 04:45:26 AM UTC 24 Aug 23 04:45:58 AM UTC 24 165157666116 ps
T320 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt.442874445 Aug 23 04:40:37 AM UTC 24 Aug 23 04:46:05 AM UTC 24 160685634668 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled_fixed.3486420366 Aug 23 04:43:15 AM UTC 24 Aug 23 04:46:47 AM UTC 24 161196368590 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt.2699770482 Aug 23 04:29:05 AM UTC 24 Aug 23 04:46:53 AM UTC 24 492396847992 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt.2000436979 Aug 23 04:34:57 AM UTC 24 Aug 23 04:46:57 AM UTC 24 328023038693 ps
T430 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_poweron_counter.1357162973 Aug 23 04:46:54 AM UTC 24 Aug 23 04:46:58 AM UTC 24 4213742709 ps
T352 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_fsm_reset.1030850394 Aug 23 04:39:57 AM UTC 24 Aug 23 04:47:03 AM UTC 24 130122246978 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1519196114 Aug 23 04:41:28 AM UTC 24 Aug 23 04:47:09 AM UTC 24 615033392131 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.543199801 Aug 23 04:47:04 AM UTC 24 Aug 23 04:47:15 AM UTC 24 3882944744 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup.4084987071 Aug 23 04:44:19 AM UTC 24 Aug 23 04:47:16 AM UTC 24 176250224979 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_alert_test.1567137080 Aug 23 04:47:16 AM UTC 24 Aug 23 04:47:18 AM UTC 24 469179260 ps
T433 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_smoke.1701901740 Aug 23 04:47:17 AM UTC 24 Aug 23 04:47:22 AM UTC 24 5861745735 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_both.4043918544 Aug 23 04:42:06 AM UTC 24 Aug 23 04:47:34 AM UTC 24 163172630913 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.3044304103 Aug 23 04:36:44 AM UTC 24 Aug 23 04:48:07 AM UTC 24 350112955853 ps
T434 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt_fixed.746808105 Aug 23 04:45:34 AM UTC 24 Aug 23 04:48:09 AM UTC 24 156500786367 ps
T435 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_lowpower_counter.1139771642 Aug 23 04:46:58 AM UTC 24 Aug 23 04:48:26 AM UTC 24 38106614284 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled_fixed.942586742 Aug 23 04:45:18 AM UTC 24 Aug 23 04:49:30 AM UTC 24 491781375607 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all.3430356237 Aug 23 04:34:42 AM UTC 24 Aug 23 04:49:31 AM UTC 24 429768527341 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup.1250095668 Aug 23 04:38:01 AM UTC 24 Aug 23 04:49:55 AM UTC 24 617143072982 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all.3710680075 Aug 23 04:42:55 AM UTC 24 Aug 23 04:50:01 AM UTC 24 76349219312 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup.3211698944 Aug 23 04:48:10 AM UTC 24 Aug 23 04:50:03 AM UTC 24 564171792395 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_poweron_counter.3359248657 Aug 23 04:49:55 AM UTC 24 Aug 23 04:50:07 AM UTC 24 4563469411 ps
T438 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt_fixed.4156695764 Aug 23 04:37:59 AM UTC 24 Aug 23 04:50:07 AM UTC 24 326862453759 ps
T439 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled_fixed.3705518254 Aug 23 04:33:26 AM UTC 24 Aug 23 04:50:09 AM UTC 24 490905461961 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_clock_gating.54270486 Aug 23 04:44:30 AM UTC 24 Aug 23 04:50:11 AM UTC 24 157371071050 ps
T440 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_alert_test.1677150260 Aug 23 04:50:10 AM UTC 24 Aug 23 04:50:12 AM UTC 24 352914146 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.977994017 Aug 23 04:50:08 AM UTC 24 Aug 23 04:50:13 AM UTC 24 3970108164 ps
T441 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_fsm_reset.2814244852 Aug 23 04:42:46 AM UTC 24 Aug 23 04:50:15 AM UTC 24 90117313532 ps
T442 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_smoke.2120082355 Aug 23 04:50:12 AM UTC 24 Aug 23 04:50:20 AM UTC 24 5614619600 ps
T443 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all.4103637870 Aug 23 04:50:08 AM UTC 24 Aug 23 04:50:23 AM UTC 24 11840344555 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt.2002773540 Aug 23 04:47:35 AM UTC 24 Aug 23 04:50:42 AM UTC 24 162151105372 ps
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