Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22634

1

T1

20

T2

20

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19063

1

T1

20

T2

20

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3571

1

T14

14

T15

13

T34

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17186

1

T1

20

T2

20

T4

20

auto[1]

5448

1

T5

5

T7

11

T10

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18984

1

T1

20

T2

20

T4

20

auto[1]

3650

1

T5

4

T7

3

T8

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	15	1			T218	15		-	-		-	-
values[0]	69	1			T219	12		T156	5		T193	29
values[1]	638	1			T59	10		T135	8		T134	11
values[2]	650	1			T14	14		T17	1		T34	11
values[3]	712	1			T84	14		T59	19		T60	22
values[4]	633	1			T10	16		T35	5		T42	20
values[5]	696	1			T15	13		T82	8		T201	1
values[6]	568	1			T200	1		T141	1		T220	1
values[7]	810	1			T41	2		T31	12		T59	21
values[8]	685	1			T13	18		T34	1		T36	2
values[9]	3193	1			T5	5		T7	11		T8	3
minimum	13965	1			T1	20		T2	20		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	801	1			T17	1		T42	8		T59	10
values[1]	683	1			T14	14		T34	11		T41	25
values[2]	768	1			T35	5		T84	14		T133	9
values[3]	612	1			T10	16		T42	20		T82	8
values[4]	674	1			T15	13		T201	1		T136	5
values[5]	719	1			T200	1		T141	1		T220	2
values[6]	2881	1			T5	5		T12	12		T16	47
values[7]	610	1			T13	18		T36	2		T132	5
values[8]	798	1			T7	11		T221	7		T138	6
values[9]	122	1			T8	3		T84	16		T60	14
minimum	13966	1			T1	20		T2	20		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18481

1

T1

20

T2

20

T4

20

auto[1]

4153

1

T7

3

T8

1

T10

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T17	1		T42	8		T135	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T59	8		T137	16		T222	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T84	13		T60	11		T165	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T14	8		T34	1		T41	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T223	1		T191	16		T50	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T35	5		T84	14		T133	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T10	8		T42	20		T82	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T224	1		T139	1		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T136	1		T160	1		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T15	1		T201	1		T224	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T220	2		T38	1		T225	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T200	1		T141	1		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1587	1			T5	1		T12	12		T16	47
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T31	1		T59	9		T205	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T13	18		T36	2		T165	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T132	3		T21	4		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T7	8		T221	4		T142	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T138	6		T226	17		T227	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T8	2		T84	16		T60	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T228	1		T24	2		T229	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13868	1			T1	20		T2	20		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T135	7		T151	4		T230	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T59	2		T137	15		T231	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T60	11		T165	12		T226	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T14	6		T34	10		T41	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T191	18		T179	9		T232	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T50	14		T233	10		T192	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T10	8		T82	7		T129	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T224	1		T234	16		T235	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T136	4		T160	11		T225	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T15	12		T224	9		T236	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T225	6		T167	9		T91	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T139	13		T207	7		T235	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	890	1			T5	4		T41	1		T83	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T31	11		T59	12		T183	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T165	7		T237	7		T234	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T132	2		T136	8		T142	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	3		T221	3		T142	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T227	6		T167	11		T88	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T8	1		T60	2		T39	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T229	6		T238	5		T239	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T36	2		T38	1		T130	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T218	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T219	12		T156	3		T240	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T193	20		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T135	1		T134	11		T138	26
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T59	8		T222	6		T231	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T17	1		T42	8		T84	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T14	8		T34	1		T41	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T60	11		T191	16		T50	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T84	14		T59	10		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T10	8		T42	20		T133	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T35	5		T224	1		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T82	1		T136	1		T129	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T15	1		T201	1		T224	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T220	1		T130	1		T140	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T200	1		T141	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T41	1		T220	1		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T31	1		T59	9		T205	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T13	18		T34	1		T36	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T132	3		T21	4		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1707	1			T5	1		T7	8		T8	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	351	1			T138	6		T226	17		T142	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13867	1			T1	20		T2	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T218	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T156	2		T240	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T193	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T135	7		T151	4		T226	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T59	2		T231	12		T32	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T165	12		T154	12		T241	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T14	6		T34	10		T41	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T60	11		T191	18		T179	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T59	9		T50	14		T192	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T10	8		T133	6		T60	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T224	1		T234	16		T233	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T82	7		T136	4		T129	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T15	12		T224	9		T242	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T91	14		T243	13		T199	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T139	13		T244	12		T236	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T41	1		T225	6		T244	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T31	11		T59	12		T207	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T165	7		T192	5		T245	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T132	2		T136	8		T183	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	933	1			T5	4		T7	3		T8	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T142	11		T227	19		T167	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T36	2		T38	1		T130	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T17	1		T42	1		T135	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T59	3		T137	16		T222	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T84	1		T60	12		T165	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T14	7		T34	11		T41	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T223	1		T191	19		T50	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T35	4		T84	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T10	9		T42	1		T82	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T224	2		T139	1		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T136	5		T160	12		T225	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T15	13		T201	1		T224	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T220	2		T38	1		T225	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T200	1		T141	1		T139	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1209	1			T5	5		T12	1		T16	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T31	12		T59	13		T205	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T13	1		T36	2		T165	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T132	3		T21	3		T136	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T7	8		T221	4		T142	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T138	1		T226	1		T227	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T8	2		T84	1		T60	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T228	1		T24	2		T229	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13966	1			T1	20		T2	20		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T42	7		T134	10		T138	24
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T59	7		T137	15		T222	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T84	12		T60	10		T165	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T14	7		T41	12		T132	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T191	15		T179	11		T232	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T35	1		T84	13		T133	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T10	7		T42	19		T129	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T234	15		T228	3		T246	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T140	15		T247	16		T248	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T236	12		T242	6		T246	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T225	7		T249	13		T167	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T166	13		T207	4		T167	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1268	1			T12	11		T16	44		T171	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T59	8		T183	1		T244	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T13	17		T165	10		T237	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T132	2		T21	1		T222	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T7	3		T221	3		T142	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T138	5		T226	16		T227	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T8	1		T84	15		T60	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T229	2		T238	4		T250	16

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T218	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T219	1		T156	3		T240	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T193	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T135	8		T134	1		T138	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T59	3		T222	1		T231	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T17	1		T42	1		T84	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T14	7		T34	11		T41	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T60	12		T191	19		T50	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T84	1		T59	10		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T10	9		T42	1		T133	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T35	4		T224	2		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T82	8		T136	5		T129	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T15	13		T201	1		T224	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T220	1		T130	1		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T200	1		T141	1		T139	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T41	2		T220	1		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T31	12		T59	13		T205	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T13	1		T34	1		T36	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T132	3		T21	3		T136	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1283	1			T5	5		T7	8		T8	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T138	1		T226	1		T142	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13965	1			T1	20		T2	20		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T219	11		T156	2		T240	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T193	19		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T134	10		T138	24		T151	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T59	7		T222	5		T143	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T42	7		T84	12		T165	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T14	7		T41	12		T132	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T60	10		T191	15		T179	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T84	13		T59	9		T50	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T10	7		T42	19		T133	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T35	1		T251	13		T234	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T129	16		T247	16		T248	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T242	6		T228	3		T246	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T140	15		T91	13		T252	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T244	10		T236	12		T167	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T225	7		T244	12		T249	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T59	8		T166	13		T207	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T13	17		T165	10		T253	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T132	2		T21	1		T222	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1357	1			T7	3		T8	1		T12	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T138	5		T226	16		T142	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18481

1

T1

20

T2

20

T4

20

auto[1]

auto[0]

4153

1

T7

3

T8

1

T10

7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22634

1

T1

20

T2

20

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

18929

1

T1

20

T2

20

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3705

1

T7

11

T8

3

T13

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16905

1

T1

20

T2

20

T4

20

auto[1]

5729

1

T5

5

T7

11

T12

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18984

1

T1

20

T2

20

T4

20

auto[1]

3650

1

T5

4

T7

3

T8

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	10	1			T177	10		-	-		-	-
values[0]	22	1			T228	1		T148	8		T254	1
values[1]	758	1			T41	25		T42	8		T59	21
values[2]	599	1			T34	12		T224	2		T60	14
values[3]	660	1			T14	14		T84	13		T36	2
values[4]	704	1			T7	11		T17	1		T35	5
values[5]	2928	1			T5	5		T12	12		T16	47
values[6]	641	1			T10	16		T13	18		T15	13
values[7]	517	1			T82	8		T59	19		T140	1
values[8]	519	1			T172	1		T255	1		T227	18
values[9]	1311	1			T8	3		T41	2		T31	12
minimum	13965	1			T1	20		T2	20		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	873	1			T42	8		T59	21		T141	1
values[1]	667	1			T34	12		T84	13		T36	2
values[2]	766	1			T14	14		T137	31		T141	1
values[3]	2842	1			T5	5		T7	11		T12	12
values[4]	680	1			T15	13		T221	7		T132	28
values[5]	602	1			T10	16		T13	18		T42	20
values[6]	415	1			T82	8		T201	1		T59	19
values[7]	604	1			T8	3		T41	2		T133	13
values[8]	969	1			T84	14		T136	14		T133	14
values[9]	226	1			T31	12		T201	1		T138	10
minimum	13990	1			T1	20		T2	20		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18481

1

T1

20

T2

20

T4

20

auto[1]

4153

1

T7

3

T8

1

T10

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T42	8		T59	9		T133	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T141	1		T129	17		T151	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T34	1		T36	2		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T34	1		T84	13		T21	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T223	1		T166	14		T234	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T14	8		T137	16		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1556	1			T5	1		T12	12		T16	47
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T7	8		T35	5		T200	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T15	1		T138	22		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T221	4		T132	17		T237	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T10	8		T84	16		T60	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T13	18		T42	20		T220	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T201	1		T256	1		T29	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T82	1		T59	10		T233	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T41	1		T133	7		T172	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T8	2		T38	6		T255	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T136	1		T133	7		T191	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T84	14		T136	1		T223	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T31	1		T248	9		T144	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T201	1		T138	10		T257	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13867	1			T1	20		T2	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T41	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T59	12		T139	3		T50	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T129	16		T151	4		T39	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T34	10		T135	7		T60	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T224	10		T139	13		T167	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T234	11		T147	12		T258	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T14	6		T137	15		T60	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	896	1			T5	4		T83	10		T259	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T7	3		T227	6		T236	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T15	12		T235	9		T145	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T221	3		T132	11		T237	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T10	8		T60	1		T165	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T146	7		T260	18		T168	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T29	1		T218	5		T261	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T82	7		T59	9		T233	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T41	1		T133	6		T227	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T8	1		T38	3		T192	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T136	8		T133	7		T191	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T136	4		T50	14		T244	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T31	11		T248	9		T144	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T25	3		T262	14		T263	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T36	2		T38	1		T130	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T41	12		-	-		-	-