Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22634

1

T1

20

T2

20

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19104

1

T1

20

T2

20

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3530

1

T7

11

T13

18

T14

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16682

1

T1

20

T2

20

T4

20

auto[1]

5952

1

T5

5

T7

11

T12

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18984

1

T1

20

T2

20

T4

20

auto[1]

3650

1

T5

4

T7

3

T8

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	271	1			T10	16		T201	1		T222	14
values[0]	33	1			T136	9		T272	1		T334	23
values[1]	572	1			T84	16		T201	1		T221	7
values[2]	721	1			T8	3		T34	11		T82	8
values[3]	661	1			T14	14		T132	5		T165	18
values[4]	602	1			T36	2		T133	9		T224	10
values[5]	578	1			T41	25		T31	12		T59	10
values[6]	752	1			T7	11		T15	13		T41	2
values[7]	705	1			T17	1		T224	2		T220	1
values[8]	2847	1			T5	5		T12	12		T16	47
values[9]	927	1			T13	18		T34	1		T35	5
minimum	13965	1			T1	20		T2	20		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	706	1			T84	16		T201	1		T221	7
values[1]	732	1			T8	3		T34	11		T82	8
values[2]	490	1			T132	5		T257	1		T226	17
values[3]	666	1			T14	14		T36	2		T136	5
values[4]	621	1			T41	27		T31	12		T59	10
values[5]	808	1			T7	11		T15	13		T141	1
values[6]	2843	1			T5	5		T12	12		T16	47
values[7]	583	1			T42	8		T84	13		T132	23
values[8]	941	1			T10	16		T13	18		T34	1
values[9]	150	1			T84	14		T274	2		T230	5
minimum	14094	1			T1	20		T2	20		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18481

1

T1

20

T2

20

T4

20

auto[1]

4153

1

T7

3

T8

1

T10

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T84	16		T135	1		T257	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T201	1		T221	4		T38	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T8	2		T165	11		T244	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T34	1		T82	1		T133	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T257	1		T275	1		T235	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T132	3		T226	17		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T36	2		T223	1		T151	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T14	8		T136	1		T133	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T31	1		T165	12		T207	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T41	14		T59	8		T219	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T138	6		T222	6		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T7	8		T15	1		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1586	1			T5	1		T12	12		T16	47
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T224	1		T225	8		T253	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T42	8		T21	4		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T84	13		T132	14		T133	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T10	8		T34	1		T42	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T13	18		T35	5		T201	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T274	2		T276	1		T88	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T84	14		T230	3		T167	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13934	1			T1	20		T2	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T223	1		T140	1		T172	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T135	7		T236	14		T167	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T221	3		T38	3		T50	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T8	1		T165	7		T244	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T34	10		T82	7		T133	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T235	11		T277	9		T154	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T132	2		T139	13		T142	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T151	4		T225	5		T277	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T14	6		T136	4		T224	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T31	11		T165	12		T207	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T41	13		T59	2		T229	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T183	1		T227	6		T247	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T7	3		T15	12		T60	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	886	1			T5	4		T83	10		T259	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T224	1		T225	6		T284	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T160	11		T139	3		T88	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T132	9		T133	6		T39	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T10	8		T59	9		T129	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T59	12		T179	9		T237	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T88	11		T279	10		T335	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T230	2		T167	9		T282	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T36	2		T136	8		T38	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T336	5		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T10	8		T222	14		T275	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T201	1		T230	3		T143	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T136	1		T272	1		T334	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T84	16		T135	1		T257	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T201	1		T221	4		T223	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T8	2		T244	5		T281	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T34	1		T82	1		T133	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T165	11		T257	1		T235	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T14	8		T132	3		T191	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T36	2		T223	1		T151	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T133	9		T224	1		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T31	1		T165	12		T225	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T41	13		T59	8		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T138	6		T222	6		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T7	8		T15	1		T41	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T17	1		T220	1		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T224	1		T225	8		T172	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1605	1			T5	1		T12	12		T16	47
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T132	14		T220	1		T142	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T34	1		T42	20		T200	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T13	18		T35	5		T84	27
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13867	1			T1	20		T2	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T10	8		T88	11		T155	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T230	2		T167	9		T153	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T136	8		T334	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T135	7		T235	9		T236	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T221	3		T248	8		T271	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T8	1		T244	6		T281	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T34	10		T82	7		T133	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T165	7		T235	11		T242	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T14	6		T132	2		T191	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T151	4		T277	6		T32	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T224	9		T91	14		T246	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T31	11		T165	12		T225	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T41	12		T59	2		T136	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T247	14		T236	12		T305	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T7	3		T15	12		T41	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T183	1		T227	19		T248	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T224	1		T225	6		T284	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	905	1			T5	4		T83	10		T259	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T132	9		T142	9		T50	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T59	9		T129	16		T60	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T59	12		T133	6		T39	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T36	2		T38	1		T130	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T84	1		T135	8		T257	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T201	1		T221	4		T38	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T8	2		T165	8		T244	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T34	11		T82	8		T133	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T257	1		T275	1		T235	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T132	3		T226	1		T139	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T36	2		T223	1		T151	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T14	7		T136	5		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T31	12		T165	13		T207	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T41	15		T59	3		T219	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T138	1		T222	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T7	8		T15	13		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1205	1			T5	5		T12	1		T16	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T224	2		T225	7		T253	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T42	1		T21	3		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T84	1		T132	10		T133	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T10	9		T34	1		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T13	1		T35	4		T201	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T274	2		T276	1		T88	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T84	1		T230	3		T167	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14019	1			T1	20		T2	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T223	1		T140	1		T172	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T84	15		T197	17		T236	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T221	3		T38	3		T244	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T8	1		T165	10		T244	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T133	6		T191	15		T234	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T245	11		T168	4		T85	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T132	2		T226	16		T142	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T151	4		T140	15		T32	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T14	7		T133	8		T143	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T165	11		T207	4		T167	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T41	12		T59	7		T219	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T138	5		T222	5		T183	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T7	3		T60	11		T138	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1267	1			T12	11		T16	44		T171	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T225	7		T253	11		T144	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T42	7		T21	1		T247	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T84	12		T132	13		T133	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T10	7		T42	19		T59	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T13	17		T35	1		T59	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T88	10		T279	11		T176	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T84	13		T230	2		T167	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T197	4		T280	6		T173	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T336	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T10	9		T222	1		T275	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T201	1		T230	3		T143	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T136	9		T272	1		T334	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T84	1		T135	8		T257	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T201	1		T221	4		T223	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T8	2		T244	7		T281	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T34	11		T82	8		T133	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T165	8		T257	1		T235	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T14	7		T132	3		T191	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T36	2		T223	1		T151	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T133	1		T224	10		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T31	12		T165	13		T225	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T41	13		T59	3		T136	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T138	1		T222	1		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T7	8		T15	13		T41	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T17	1		T220	1		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T224	2		T225	7		T172	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1229	1			T5	5		T12	1		T16	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T132	10		T220	1		T142	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T34	1		T42	1		T200	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T13	1		T35	4		T84	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13965	1			T1	20		T2	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T10	7		T222	13		T88	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T230	2		T143	14		T167	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T334	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T84	15		T197	4		T236	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T221	3		T248	8		T92	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T8	1		T244	4		T197	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T133	6		T38	3		T142	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T165	10		T242	6		T252	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T14	7		T132	2		T191	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T151	4		T32	15		T246	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T133	8		T226	16		T143	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T165	11		T140	15		T207	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T41	12		T59	7		T285	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T138	5		T222	5		T251	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T7	3		T60	11		T138	24
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T183	1		T166	13		T227	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T225	7		T166	16		T253	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1281	1			T12	11		T16	44		T42	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T132	13		T142	9		T50	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T42	19		T59	9		T129	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T13	17		T35	1		T84	25

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18481

1

T1

20

T2

20

T4

20

auto[1]

auto[0]

4153

1

T7

3

T8

1

T10

7