Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22634

1

T1

20

T2

20

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19248

1

T1

20

T2

20

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3386

1

T7

11

T8

3

T13

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17347

1

T1

20

T2

20

T4

20

auto[1]

5287

1

T5

5

T8

3

T12

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18984

1

T1

20

T2

20

T4

20

auto[1]

3650

1

T5

4

T7

3

T8

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	255	1			T13	18		T84	16		T132	5
values[0]	56	1			T231	1		T271	33		T329	15
values[1]	717	1			T201	1		T135	8		T60	36
values[2]	647	1			T42	20		T59	10		T138	6
values[3]	590	1			T221	7		T141	1		T133	9
values[4]	2880	1			T5	5		T10	16		T12	12
values[5]	518	1			T7	11		T35	5		T42	8
values[6]	570	1			T201	1		T38	9		T165	2
values[7]	781	1			T8	3		T14	14		T15	13
values[8]	685	1			T59	21		T136	9		T137	31
values[9]	970	1			T34	1		T41	27		T82	8
minimum	13965	1			T1	20		T2	20		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	752	1			T42	20		T201	1		T60	36
values[1]	652	1			T59	10		T141	1		T133	9
values[2]	531	1			T10	16		T221	7		T224	10
values[3]	2891	1			T5	5		T7	11		T12	12
values[4]	419	1			T35	5		T42	8		T138	16
values[5]	686	1			T14	14		T31	12		T200	1
values[6]	774	1			T8	3		T15	13		T17	1
values[7]	666	1			T41	25		T82	8		T136	9
values[8]	1037	1			T13	18		T34	1		T41	2
values[9]	33	1			T197	5		T284	10		T285	14
minimum	14193	1			T1	20		T2	20		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18481

1

T1

20

T2

20

T4

20

auto[1]

4153

1

T7

3

T8

1

T10

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T60	12		T40	1		T143	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T42	20		T201	1		T60	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T141	1		T133	9		T138	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T59	8		T244	5		T227	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T10	8		T224	1		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T221	4		T165	11		T222	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1584	1			T5	1		T12	12		T16	47
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T7	8		T84	14		T132	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T35	5		T42	8		T226	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T138	16		T38	6		T244	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T140	16		T142	10		T50	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T14	8		T31	1		T200	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T17	1		T34	1		T59	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T8	2		T15	1		T223	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T41	13		T136	1		T139	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T82	1		T134	11		T226	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T34	1		T84	29		T36	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T13	18		T41	1		T224	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T197	5		T284	1		T285	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T330	1		-	-		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13934	1			T1	20		T2	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T247	9		T256	1		T260	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T60	2		T321	9		T147	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T60	11		T165	12		T234	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T160	11		T183	1		T320	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T59	2		T244	6		T227	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T10	8		T224	9		T145	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T221	3		T165	7		T225	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	881	1			T5	4		T83	10		T259	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T7	3		T132	9		T129	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T241	9		T280	2		T218	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T38	3		T244	12		T32	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T142	9		T50	12		T244	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T14	6		T31	11		T165	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T34	10		T59	12		T136	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T8	1		T15	12		T237	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T41	12		T136	8		T139	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T82	7		T226	8		T207	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T132	2		T59	9		T133	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T41	1		T224	1		T60	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T284	9		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T36	2		T135	7		T38	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T260	6		T189	13		T194	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T84	16		T132	3		T231	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T13	18		T224	1		T225	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T231	1		T271	17		T329	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T331	1		T332	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T135	1		T60	12		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T201	1		T60	11		T166	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T138	6		T160	1		T183	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T42	20		T59	8		T165	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T141	1		T133	9		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T221	4		T165	11		T222	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1607	1			T5	1		T10	8		T12	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T84	14		T132	14		T21	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T35	5		T42	8		T23	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T7	8		T138	16		T244	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T226	17		T140	16		T142	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T201	1		T38	6		T165	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T17	1		T34	1		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T8	2		T14	8		T15	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T59	9		T136	1		T137	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T134	11		T138	10		T226	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T34	1		T41	13		T84	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T41	1		T82	1		T60	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13867	1			T1	20		T2	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T132	2		T231	12		T227	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T224	1		T225	6		T96	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T271	16		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T135	7		T60	2		T277	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T60	11		T88	11		T260	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T160	11		T183	1		T321	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T59	2		T165	12		T244	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T320	13		T153	12		T307	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T221	3		T165	7		T225	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	894	1			T5	4		T10	8		T83	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T132	9		T129	16		T167	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T305	14		T280	2		T218	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T7	3		T244	12		T234	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T142	9		T244	12		T229	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T38	3		T165	1		T39	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T34	10		T136	4		T133	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T8	1		T14	6		T15	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T59	12		T136	8		T137	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T226	8		T207	7		T235	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T41	12		T59	9		T133	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T41	1		T82	7		T60	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T36	2		T38	1		T130	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T60	3		T40	1		T143	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T42	1		T201	1		T60	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T141	1		T133	1		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T59	3		T244	7		T227	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T10	9		T224	10		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T221	4		T165	8		T222	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1202	1			T5	5		T12	1		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T7	8		T84	1		T132	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T35	4		T42	1		T226	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T138	1		T38	6		T244	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T140	1		T142	10		T50	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T14	7		T31	12		T200	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T17	1		T34	11		T59	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T8	2		T15	13		T223	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T41	13		T136	9		T139	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T82	8		T134	1		T226	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T34	1		T84	2		T36	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T13	1		T41	2		T224	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T197	1		T284	10		T285	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T330	1		-	-		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14080	1			T1	20		T2	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T247	1		T256	1		T260	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T60	11		T143	16		T329	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T42	19		T60	10		T165	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T133	8		T138	5		T183	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T59	7		T244	4		T227	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T10	7		T145	9		T307	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T221	3		T165	10		T222	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1263	1			T12	11		T16	44		T171	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T7	3		T84	13		T132	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T35	1		T42	7		T226	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T138	15		T38	3		T244	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T140	15		T142	9		T244	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T14	7		T39	1		T232	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T59	8		T137	15		T133	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T8	1		T138	9		T237	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T41	12		T179	11		T249	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T134	10		T226	8		T140	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T84	27		T132	2		T59	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T13	17		T151	4		T225	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T197	4		T285	13		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T283	5		T271	16		T289	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T247	8		T337	9		T189	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T84	1		T132	3		T231	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T13	1		T224	2		T225	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T231	1		T271	17		T329	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T331	1		T332	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T135	8		T60	3		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T201	1		T60	12		T166	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T138	1		T160	12		T183	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T42	1		T59	3		T165	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T141	1		T133	1		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T221	4		T165	8		T222	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1219	1			T5	5		T10	9		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T84	1		T132	10		T21	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T35	4		T42	1		T23	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T7	8		T138	1		T244	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T226	1		T140	1		T142	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T201	1		T38	6		T165	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T17	1		T34	11		T136	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T8	2		T14	7		T15	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T59	13		T136	9		T137	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T134	1		T138	1		T226	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T34	1		T41	13		T84	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T41	2		T82	8		T60	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13965	1			T1	20		T2	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T84	15		T132	2		T227	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T13	17		T225	7		T96	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T271	16		T329	14		T338	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T60	11		T283	5		T289	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T60	10		T166	16		T247	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T138	5		T183	1		T143	33
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T42	19		T59	7		T165	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T133	8		T307	9		T252	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T221	3		T165	10		T222	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1282	1			T10	7		T12	11		T16	44
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T84	13		T132	13		T21	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T35	1		T42	7		T326	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T7	3		T138	15		T244	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T226	16		T140	15		T142	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T38	3		T39	1		T247	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T133	6		T191	15		T249	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T8	1		T14	7		T232	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T59	8		T137	15		T249	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T134	10		T138	9		T226	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T41	12		T84	12		T59	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T151	4		T143	14		T192	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18481

1

T1

20

T2

20

T4

20

auto[1]

auto[0]

4153

1

T7

3

T8

1

T10

7