Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22634

1

T1

20

T2

20

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

17322

1

T1

20

T2

20

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

5312

1

T5

5

T7

11

T8

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17014

1

T1

20

T2

20

T4

20

auto[1]

5620

1

T5

5

T8

3

T12

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18984

1

T1

20

T2

20

T4

20

auto[1]

3650

1

T5

4

T7

3

T8

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	296	1			T10	16		T132	5		T226	17
values[0]	36	1			T229	2		T156	18		T297	16
values[1]	763	1			T13	18		T14	14		T41	2
values[2]	647	1			T34	11		T84	16		T200	1
values[3]	559	1			T7	11		T17	1		T34	1
values[4]	774	1			T201	1		T59	19		T137	31
values[5]	572	1			T84	14		T135	8		T133	9
values[6]	646	1			T60	14		T160	12		T225	6
values[7]	651	1			T8	3		T41	25		T42	20
values[8]	663	1			T15	13		T35	5		T42	8
values[9]	3062	1			T5	5		T12	12		T16	47
minimum	13965	1			T1	20		T2	20		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	658	1			T14	14		T82	8		T84	13
values[1]	2831	1			T5	5		T12	12		T16	47
values[2]	607	1			T7	11		T17	1		T34	1
values[3]	609	1			T59	19		T137	31		T60	22
values[4]	695	1			T84	14		T135	8		T133	9
values[5]	651	1			T8	3		T60	14		T138	6
values[6]	731	1			T41	25		T42	20		T201	1
values[7]	559	1			T15	13		T35	5		T42	8
values[8]	964	1			T10	16		T31	12		T132	5
values[9]	70	1			T179	21		T258	2		T339	1
minimum	14259	1			T1	20		T2	20		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18481

1

T1

20

T2

20

T4

20

auto[1]

4153

1

T7

3

T8

1

T10

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T84	13		T200	1		T132	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T14	8		T82	1		T36	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T34	1		T59	9		T138	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1575	1			T5	1		T12	12		T16	47
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T17	1		T34	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T7	8		T201	1		T59	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T137	16		T140	3		T235	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T59	10		T60	11		T39	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T60	1		T220	1		T140	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T84	14		T135	1		T133	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T60	12		T165	11		T257	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T8	2		T138	6		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T41	13		T201	1		T129	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T42	20		T141	1		T142	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T139	1		T231	1		T172	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T15	1		T35	5		T42	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T136	1		T138	16		T222	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T10	8		T31	1		T132	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T258	1		T339	1		T291	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T179	12		T288	9		T340	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13976	1			T1	20		T2	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T223	1		T40	1		T275	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T132	9		T133	7		T38	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T14	6		T82	7		T221	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T34	10		T59	12		T167	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	913	1			T5	4		T83	10		T259	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T224	10		T151	4		T237	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T7	3		T59	2		T136	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T137	15		T235	9		T145	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T59	9		T60	11		T39	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T60	1		T289	3		T341	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T135	7		T225	5		T207	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T60	2		T165	7		T191	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T8	1		T160	11		T50	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T41	12		T129	16		T225	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T142	11		T50	14		T241	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T232	15		T234	16		T144	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T15	12		T183	1		T153	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T136	8		T237	7		T227	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T10	8		T31	11		T132	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T258	1		T291	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T179	9		T288	16		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T41	1		T36	2		T38	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T248	10		T314	15		T325	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T166	18		T237	8		T147	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T10	8		T132	3		T226	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T229	1		T156	11		T297	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T13	18		T41	1		T84	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T14	8		T82	1		T221	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T34	1		T200	1		T59	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T84	16		T36	2		T165	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T17	1		T34	1		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T7	8		T59	8		T21	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T137	16		T220	1		T140	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T201	1		T59	10		T60	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T60	1		T220	1		T140	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T84	14		T135	1		T133	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T60	12		T257	1		T191	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T160	1		T225	1		T50	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T41	13		T201	1		T165	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T8	2		T42	20		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T129	17		T225	8		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T15	1		T35	5		T42	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T136	1		T138	16		T222	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1676	1			T5	1		T12	12		T16	47
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13867	1			T1	20		T2	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T237	7		T147	10		T280	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T10	8		T132	2		T226	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T229	1		T156	7		T297	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T41	1		T132	9		T133	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T14	6		T82	7		T221	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T34	10		T59	12		T38	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T165	1		T234	11		T321	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T224	10		T151	4		T237	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T7	3		T59	2		T136	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T137	15		T235	9		T277	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T59	9		T60	11		T248	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T60	1		T341	10		T293	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T135	7		T39	1		T231	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T60	2		T191	18		T235	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T160	11		T225	5		T50	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T41	12		T165	7		T139	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T8	1		T142	11		T244	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T129	16		T225	6		T232	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T15	12		T50	14		T183	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T136	8		T234	16		T227	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	965	1			T5	4		T83	10		T31	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T36	2		T38	1		T130	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T84	1		T200	1		T132	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T14	7		T82	8		T36	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T34	11		T59	13		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1225	1			T5	5		T12	1		T16	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T17	1		T34	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T7	8		T201	1		T59	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T137	16		T140	1		T235	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T59	10		T60	12		T39	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T60	2		T220	1		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T84	1		T135	8		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T60	3		T165	8		T257	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T8	2		T138	1		T160	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T41	13		T201	1		T129	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T42	1		T141	1		T142	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T139	1		T231	1		T172	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T15	13		T35	4		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T136	9		T138	1		T222	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T10	9		T31	12		T132	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T258	2		T339	1		T291	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T179	10		T288	17		T340	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14058	1			T1	20		T2	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T223	1		T40	1		T275	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T84	12		T132	13		T133	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T14	7		T221	3		T165	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T59	8		T138	9		T222	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1263	1			T12	11		T16	44		T84	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T151	4		T237	8		T249	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T7	3		T59	7		T134	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T137	15		T140	2		T145	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T59	9		T60	10		T39	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T140	15		T228	18		T289	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T84	13		T133	8		T226	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T60	11		T165	10		T191	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T8	1		T138	5		T244	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T41	12		T129	16		T225	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T42	19		T142	13		T50	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T232	4		T234	15		T143	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T35	1		T42	7		T183	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T138	15		T222	13		T166	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T10	7		T132	2		T133	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T291	9		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T179	11		T288	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T13	17		T233	4		T249	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T248	7		T169	14		T323	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T166	1		T237	8		T147	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T10	9		T132	3		T226	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T229	2		T156	8		T297	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T13	1		T41	2		T84	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T14	7		T82	8		T221	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T34	11		T200	1		T59	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T84	1		T36	2		T165	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T17	1		T34	1		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T7	8		T59	3		T21	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T137	16		T220	1		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T201	1		T59	10		T60	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T60	2		T220	1		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T84	1		T135	8		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T60	3		T257	1		T191	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T160	12		T225	6		T50	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T41	13		T201	1		T165	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T8	2		T42	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T129	17		T225	7		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T15	13		T35	4		T42	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T136	9		T138	1		T222	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1303	1			T5	5		T12	1		T16	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13965	1			T1	20		T2	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T166	17		T237	7		T147	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T10	7		T132	2		T226	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T156	10		T297	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T13	17		T84	12		T132	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T14	7		T221	3		T165	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T59	8		T138	9		T38	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T84	15		T234	13		T303	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T151	4		T237	8		T167	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T7	3		T59	7		T21	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T137	15		T140	2		T249	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T59	9		T60	10		T134	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T140	15		T228	18		T341	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T84	13		T133	8		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T60	11		T191	15		T145	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T298	4		T266	6		T88	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T41	12		T165	10		T230	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T8	1		T42	19		T138	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T129	16		T225	7		T232	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T35	1		T42	7		T50	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T138	15		T222	13		T234	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1338	1			T12	11		T16	44		T171	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18481

1

T1

20

T2

20

T4

20

auto[1]

auto[0]

4153

1

T7

3

T8

1

T10

7