Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22634

1

T1

20

T2

20

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19326

1

T1

20

T2

20

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3308

1

T13

18

T14

14

T15

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16828

1

T1

20

T2

20

T4

20

auto[1]

5806

1

T5

5

T7

14

T12

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18984

1

T1

20

T2

20

T4

20

auto[1]

3650

1

T5

4

T7

3

T8

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	317	1			T7	3		T35	2		T36	8
values[0]	17	1			T342	1		T299	1		T295	15
values[1]	564	1			T14	14		T141	1		T133	14
values[2]	2829	1			T5	5		T10	16		T12	12
values[3]	786	1			T34	12		T141	1		T138	22
values[4]	569	1			T17	1		T35	5		T31	12
values[5]	757	1			T42	20		T132	23		T135	8
values[6]	582	1			T7	11		T200	1		T21	4
values[7]	584	1			T15	13		T42	8		T201	1
values[8]	675	1			T82	8		T84	13		T221	7
values[9]	1257	1			T8	3		T13	18		T41	25
minimum	13697	1			T1	20		T2	20		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	706	1			T14	14		T141	1		T133	14
values[1]	2832	1			T5	5		T10	16		T12	12
values[2]	767	1			T34	12		T141	1		T129	33
values[3]	555	1			T17	1		T35	5		T31	12
values[4]	731	1			T42	20		T84	16		T137	31
values[5]	686	1			T7	11		T15	13		T200	1
values[6]	507	1			T42	8		T59	21		T136	5
values[7]	798	1			T41	25		T82	8		T84	27
values[8]	848	1			T8	3		T59	10		T60	22
values[9]	217	1			T13	18		T138	10		T225	14
minimum	13987	1			T1	20		T2	20		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18481

1

T1

20

T2

20

T4

20

auto[1]

4153

1

T7

3

T8

1

T10

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T141	1		T160	1		T233	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T14	8		T133	7		T224	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1527	1			T5	1		T10	8		T12	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T36	2		T38	1		T191	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T34	2		T129	17		T138	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T141	1		T223	1		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T35	5		T132	14		T231	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T17	1		T31	1		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T84	16		T137	16		T60	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T42	20		T222	6		T225	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T7	8		T200	1		T201	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T15	1		T133	7		T134	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T59	9		T223	1		T249	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T42	8		T136	1		T220	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T84	27		T221	4		T132	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T41	13		T82	1		T59	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T8	2		T165	1		T226	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T59	8		T60	11		T38	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T138	10		T225	8		T247	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T13	18		T139	1		T142	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13868	1			T1	20		T2	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T342	1		T156	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T160	11		T233	10		T192	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T14	6		T133	7		T224	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	855	1			T5	4		T10	8		T41	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T191	18		T142	11		T237	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T34	10		T129	16		T230	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T192	5		T278	4		T153	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T132	9		T227	13		T302	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T31	11		T135	7		T244	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T137	15		T60	1		T151	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T225	5		T50	14		T235	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T7	3		T277	9		T148	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T15	12		T133	6		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T59	12		T266	11		T248	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T136	4		T139	13		T283	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T221	3		T132	2		T165	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T41	12		T82	7		T59	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T8	1		T165	1		T226	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T59	2		T60	11		T38	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T225	6		T146	7		T303	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T142	9		T231	12		T25	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T36	2		T38	1		T130	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T156	10		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T7	3		T35	2		T36	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T301	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T295	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T342	1		T299	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T141	1		T160	1		T50	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T14	8		T133	7		T224	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1533	1			T5	1		T10	8		T12	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T36	2		T191	16		T142	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T34	2		T138	22		T166	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T141	1		T38	1		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T35	5		T84	16		T129	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T17	1		T31	1		T223	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T132	14		T137	16		T60	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T42	20		T135	1		T222	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T7	8		T200	1		T21	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T134	11		T39	2		T140	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T201	1		T59	9		T223	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T15	1		T42	8		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T84	13		T221	4		T132	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T82	1		T59	10		T133	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	446	1			T8	2		T84	14		T138	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T13	18		T41	13		T59	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13599	1			T1	20		T2	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T303	19		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T301	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T295	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T160	11		T233	10		T192	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T14	6		T133	7		T224	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	873	1			T5	4		T10	8		T41	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T191	18		T142	11		T237	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T34	10		T32	8		T305	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T153	12		T147	10		T290	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T129	16		T151	4		T230	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T31	11		T244	12		T192	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T132	9		T137	15		T60	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T135	7		T225	5		T50	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T7	3		T167	11		T154	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T39	1		T32	14		T271	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T59	12		T266	3		T248	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T15	12		T136	4		T133	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T221	3		T132	2		T139	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T82	7		T59	9		T224	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T8	1		T165	8		T225	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T41	12		T59	2		T60	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T36	2		T38	1		T130	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T141	1		T160	12		T233	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T14	7		T133	8		T224	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1172	1			T5	5		T10	9		T12	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T36	2		T38	1		T191	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T34	12		T129	17		T138	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T141	1		T223	1		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T35	4		T132	10		T231	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T17	1		T31	12		T135	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T84	1		T137	16		T60	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T42	1		T222	1		T225	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T7	8		T200	1		T201	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T15	13		T133	7		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T59	13		T223	1		T249	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T42	1		T136	5		T220	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T84	2		T221	4		T132	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T41	13		T82	8		T59	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T8	2		T165	2		T226	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T59	3		T60	12		T38	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T138	1		T225	7		T247	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T13	1		T139	1		T142	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13966	1			T1	20		T2	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T342	1		T156	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T233	4		T192	14		T270	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T14	7		T133	6		T60	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1210	1			T10	7		T12	11		T16	44
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T191	15		T142	13		T166	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T129	16		T138	20		T166	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T251	13		T192	4		T173	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T35	1		T132	13		T227	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T244	10		T236	12		T241	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T84	15		T137	15		T151	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T42	19		T222	5		T50	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T7	3		T21	1		T166	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T133	6		T134	10		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T59	8		T249	13		T266	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T42	7		T285	13		T219	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T84	25		T221	3		T132	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T41	12		T59	9		T133	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T8	1		T226	8		T232	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T59	7		T60	10		T38	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T138	9		T225	7		T247	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T13	17		T142	9		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T156	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T7	3		T35	2		T36	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T301	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T295	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T342	1		T299	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T141	1		T160	12		T50	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T14	7		T133	8		T224	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1194	1			T5	5		T10	9		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T36	2		T191	19		T142	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T34	12		T138	2		T166	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T141	1		T38	1		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T35	4		T84	1		T129	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T17	1		T31	12		T223	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T132	10		T137	16		T60	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T42	1		T135	8		T222	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T7	8		T200	1		T21	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T134	1		T39	2		T140	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T201	1		T59	13		T223	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T15	13		T42	1		T136	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T84	1		T221	4		T132	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T82	8		T59	10		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	367	1			T8	2		T84	1		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T13	1		T41	13		T59	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13697	1			T1	20		T2	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T303	18		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T301	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T295	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T233	4		T192	14		T270	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T14	7		T133	6		T60	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1212	1			T10	7		T12	11		T16	44
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T191	15		T142	13		T166	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T138	20		T166	16		T253	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T249	13		T219	14		T147	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T35	1		T84	15		T129	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T244	10		T251	13		T192	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T132	13		T137	15		T227	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T42	19		T222	5		T50	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	3		T21	1		T166	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T134	10		T39	1		T140	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T59	8		T266	2		T248	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T42	7		T133	6		T234	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T84	12		T221	3		T132	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T59	9		T133	8		T226	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	381	1			T8	1		T84	13		T138	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T13	17		T41	12		T59	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18481

1

T1

20

T2

20

T4

20

auto[1]

auto[0]

4153

1

T7

3

T8

1

T10

7