Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22634

1

T1

20

T2

20

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19207

1

T1

20

T2

20

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3427

1

T7

11

T8

3

T13

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16737

1

T1

20

T2

20

T4

20

auto[1]

5897

1

T5

5

T7

11

T12

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18984

1

T1

20

T2

20

T4

20

auto[1]

3650

1

T5

4

T7

3

T8

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	406	1			T133	14		T138	10		T191	34
values[0]	15	1			T228	1		T264	7		T239	7
values[1]	774	1			T41	25		T42	8		T59	21
values[2]	634	1			T34	12		T84	13		T224	12
values[3]	567	1			T14	14		T36	2		T135	8
values[4]	810	1			T7	11		T17	1		T35	5
values[5]	2879	1			T5	5		T12	12		T16	47
values[6]	630	1			T10	16		T13	18		T15	13
values[7]	520	1			T82	8		T59	19		T140	1
values[8]	520	1			T8	3		T41	2		T38	9
values[9]	914	1			T31	12		T84	14		T201	1
minimum	13965	1			T1	20		T2	20		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	815	1			T42	8		T59	21		T129	33
values[1]	603	1			T34	12		T84	13		T36	2
values[2]	744	1			T14	14		T137	31		T141	1
values[3]	2870	1			T5	5		T7	11		T12	12
values[4]	711	1			T13	18		T15	13		T221	7
values[5]	546	1			T10	16		T42	20		T84	16
values[6]	477	1			T82	8		T201	1		T59	19
values[7]	611	1			T8	3		T41	2		T136	9
values[8]	971	1			T84	14		T201	1		T136	5
values[9]	183	1			T31	12		T257	1		T244	25
minimum	14103	1			T1	20		T2	20		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18481

1

T1

20

T2

20

T4

20

auto[1]

4153

1

T7

3

T8

1

T10

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T42	8		T59	9		T129	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T222	20		T50	1		T237	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T36	2		T135	1		T60	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T34	2		T84	13		T21	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T141	1		T142	10		T234	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T14	8		T137	16		T60	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1564	1			T5	1		T12	12		T16	47
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T7	8		T35	5		T200	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T15	1		T138	16		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T13	18		T221	4		T132	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T10	8		T84	16		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T42	20		T60	1		T220	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T201	1		T172	1		T256	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T82	1		T59	10		T233	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T41	1		T136	1		T227	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T8	2		T38	6		T255	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T133	14		T191	16		T50	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T84	14		T201	1		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T31	1		T174	8		T312	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T257	1		T244	13		T144	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13925	1			T1	20		T2	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T141	1		T133	9		T326	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T59	12		T129	16		T139	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T50	12		T237	10		T247	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T135	7		T60	2		T160	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T34	10		T224	10		T39	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T142	9		T234	11		T258	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T14	6		T137	15		T60	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	892	1			T5	4		T83	10		T259	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T7	3		T227	6		T236	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T15	12		T235	9		T277	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T221	3		T132	11		T237	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T10	8		T165	1		T225	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T60	1		T146	7		T260	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T29	1		T218	5		T343	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T82	7		T59	9		T233	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T41	1		T136	8		T227	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T8	1		T38	3		T227	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T133	13		T191	18		T266	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T136	4		T50	14		T234	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T31	11		T312	9		T269	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T244	12		T144	7		T25	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T41	12		T36	2		T38	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T239	6		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T133	7		T191	16		T196	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T138	10		T244	13		T242	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T228	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T264	3		T239	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T41	13		T42	8		T59	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T21	4		T141	1		T133	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T60	12		T165	11		T226	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T34	2		T84	13		T224	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T36	2		T135	1		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	8		T130	1		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T17	1		T59	8		T183	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T7	8		T35	5		T200	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1589	1			T5	1		T12	12		T16	47
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T221	4		T132	3		T138	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T10	8		T15	1		T84	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T13	18		T42	20		T132	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T140	1		T142	14		T244	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T82	1		T59	10		T233	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T41	1		T172	1		T342	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T8	2		T38	6		T255	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T31	1		T136	1		T133	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T84	14		T201	1		T136	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13867	1			T1	20		T2	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T133	7		T191	18		T266	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T244	12		T242	6		T144	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T264	4		T239	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T41	12		T59	12		T129	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T50	12		T237	10		T247	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T60	2		T165	7		T226	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T34	10		T224	10		T39	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T135	7		T160	11		T225	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T14	6		T231	12		T244	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T59	2		T183	1		T266	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T7	3		T137	15		T60	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	898	1			T5	4		T83	10		T259	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T221	3		T132	2		T237	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T10	8		T15	12		T165	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T132	9		T60	1		T207	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T142	11		T244	12		T29	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T82	7		T59	9		T233	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T41	1		T148	22		T229	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T8	1		T38	3		T227	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T31	11		T136	8		T133	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T136	4		T50	14		T234	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T36	2		T38	1		T130	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T42	1		T59	13		T129	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T222	2		T50	13		T237	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T36	2		T135	8		T60	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T34	12		T84	1		T21	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T141	1		T142	10		T234	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T14	7		T137	16		T60	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1210	1			T5	5		T12	1		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T7	8		T35	4		T200	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T15	13		T138	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T13	1		T221	4		T132	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T10	9		T84	1		T165	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T42	1		T60	2		T220	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T201	1		T172	1		T256	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T82	8		T59	10		T233	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T41	2		T136	9		T227	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T8	2		T38	6		T255	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T133	15		T191	19		T50	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T84	1		T201	1		T136	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T31	12		T174	1		T312	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T257	1		T244	13		T144	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14016	1			T1	20		T2	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T141	1		T133	1		T326	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T42	7		T59	8		T129	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T222	18		T237	8		T251	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T60	11		T165	10		T225	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T84	12		T21	1		T39	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T142	9		T234	13		T258	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T14	7		T137	15		T60	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1246	1			T12	11		T16	44		T171	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T7	3		T35	1		T140	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T138	15		T145	9		T219	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T13	17		T221	3		T132	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T10	7		T84	15		T142	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T42	19		T226	16		T298	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T29	1		T343	10		T268	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T59	9		T233	4		T143	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T227	12		T197	4		T148	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T8	1		T38	3		T249	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T133	12		T191	15		T266	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T84	13		T138	9		T50	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T174	7		T312	2		T269	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T244	12		T144	8		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T41	12		T151	4		T315	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T133	8		T326	16		T344	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T133	8		T191	19		T196	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T138	1		T244	13		T242	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T228	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T264	5		T239	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T41	13		T42	1		T59	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T21	3		T141	1		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T60	3		T165	8		T226	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T34	12		T84	1		T224	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T36	2		T135	8		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T14	7		T130	1		T231	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T17	1		T59	3		T183	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T7	8		T35	4		T200	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1215	1			T5	5		T12	1		T16	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T221	4		T132	3		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T10	9		T15	13		T84	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T13	1		T42	1		T132	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T140	1		T142	12		T244	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T82	8		T59	10		T233	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T41	2		T172	1		T342	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T8	2		T38	6		T255	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T31	12		T136	9		T133	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T84	1		T201	1		T136	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13965	1			T1	20		T2	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T133	6		T191	15		T266	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T138	9		T244	12		T242	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T264	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T41	12		T42	7		T59	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T21	1		T133	8		T222	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T60	11		T165	10		T226	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T84	12		T222	5		T39	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T225	7		T142	9		T234	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T14	7		T166	13		T244	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T59	7		T183	1		T266	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T7	3		T35	1		T137	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1272	1			T12	11		T16	44		T171	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T221	3		T132	2		T138	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T10	7		T84	15		T166	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	17		T42	19		T132	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T142	13		T244	10		T219	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T59	9		T233	4		T143	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T148	17		T229	2		T341	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T8	1		T38	3		T249	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T133	6		T227	12		T197	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T84	13		T50	15		T234	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18481

1

T1

20

T2

20

T4

20

auto[1]

auto[0]

4153

1

T7

3

T8

1

T10

7