Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22634

1

T1

20

T2

20

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

18991

1

T1

20

T2

20

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3643

1

T14

14

T15

13

T34

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17075

1

T1

20

T2

20

T4

20

auto[1]

5559

1

T5

5

T7

11

T10

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18984

1

T1

20

T2

20

T4

20

auto[1]

3650

1

T5

4

T7

3

T8

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	297	1			T84	16		T226	17		T166	17
values[0]	30	1			T193	29		T313	1		-	-
values[1]	649	1			T59	10		T135	8		T137	31
values[2]	676	1			T14	14		T17	1		T34	11
values[3]	678	1			T35	5		T84	14		T59	19
values[4]	624	1			T10	16		T42	20		T133	13
values[5]	710	1			T15	13		T82	8		T201	1
values[6]	632	1			T200	1		T141	1		T220	1
values[7]	832	1			T41	2		T31	12		T59	21
values[8]	640	1			T13	18		T34	1		T36	2
values[9]	2901	1			T5	5		T7	11		T8	3
minimum	13965	1			T1	20		T2	20		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	700	1			T17	1		T42	8		T59	10
values[1]	573	1			T14	14		T34	11		T41	25
values[2]	724	1			T35	5		T84	14		T133	9
values[3]	674	1			T10	16		T42	20		T82	8
values[4]	671	1			T15	13		T201	1		T224	10
values[5]	869	1			T200	1		T59	21		T141	1
values[6]	2764	1			T5	5		T12	12		T16	47
values[7]	605	1			T13	18		T36	2		T132	5
values[8]	804	1			T7	11		T8	3		T221	7
values[9]	115	1			T84	16		T39	3		T167	25
minimum	14135	1			T1	20		T2	20		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18481

1

T1

20

T2

20

T4

20

auto[1]

4153

1

T7

3

T8

1

T10

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T17	1		T42	8		T135	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T59	8		T137	16		T222	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T84	13		T165	12		T231	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T14	8		T34	1		T41	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T60	11		T50	1		T172	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T35	5		T84	14		T133	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T10	8		T42	20		T82	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T224	1		T139	1		T234	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T160	1		T225	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T15	1		T201	1		T224	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T220	2		T38	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T200	1		T59	9		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1569	1			T5	1		T12	12		T16	47
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T31	1		T205	1		T183	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T13	18		T36	2		T165	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T132	3		T21	4		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T7	8		T8	2		T221	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T60	12		T138	6		T226	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T84	16		T204	5		T243	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T39	2		T167	14		T256	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13928	1			T1	20		T2	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T143	17		T148	1		T189	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T135	7		T151	4		T226	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T59	2		T137	15		T231	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T165	12		T284	11		T88	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T14	6		T34	10		T41	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T60	11		T179	9		T232	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T50	14		T233	10		T192	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T10	8		T82	7		T136	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T224	1		T234	16		T235	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T160	11		T225	5		T139	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T15	12		T224	9		T242	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T244	12		T248	9		T145	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T59	12		T139	13		T244	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	851	1			T5	4		T41	1		T83	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T31	11		T183	1		T277	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T165	7		T237	7		T234	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T132	2		T136	8		T142	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	3		T8	1		T221	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T60	2		T227	6		T88	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T243	1		T312	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T39	1		T167	11		T188	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T36	2		T38	1		T130	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T148	7		T189	14		T306	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T84	16		T166	17		T271	17
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T226	17		T256	1		T32	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T313	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T193	20		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T135	1		T134	11		T138	26
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T59	8		T137	16		T222	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T17	1		T42	8		T84	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T14	8		T34	1		T41	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T60	11		T50	1		T172	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T35	5		T84	14		T59	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T10	8		T42	20		T133	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T224	1		T223	1		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T82	1		T136	1		T129	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T15	1		T201	1		T224	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T220	1		T140	16		T249	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T200	1		T141	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T41	1		T220	1		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T31	1		T59	9		T205	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T13	18		T34	1		T36	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T132	3		T136	1		T222	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1631	1			T5	1		T7	8		T8	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T21	4		T60	12		T138	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13867	1			T1	20		T2	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T271	16		T267	7		T155	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T258	14		T260	12		T238	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T193	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T135	7		T151	4		T226	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T59	2		T137	15		T231	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T165	12		T88	11		T154	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T14	6		T34	10		T41	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T60	11		T179	9		T232	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T59	9		T50	14		T192	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T10	8		T133	6		T60	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T224	1		T234	16		T233	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T82	7		T136	4		T129	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T15	12		T224	9		T235	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T247	14		T145	3		T147	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T139	13		T244	12		T236	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T41	1		T225	6		T244	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T31	11		T59	12		T207	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T165	7		T192	5		T245	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T132	2		T136	8		T142	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	878	1			T5	4		T7	3		T8	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T60	2		T39	1		T227	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T36	2		T38	1		T130	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T17	1		T42	1		T135	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T59	3		T137	16		T222	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T84	1		T165	13		T231	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T14	7		T34	11		T41	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T60	12		T50	1		T172	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T35	4		T84	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T10	9		T42	1		T82	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T224	2		T139	1		T234	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T160	12		T225	6		T139	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T15	13		T201	1		T224	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T220	2		T38	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T200	1		T59	13		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1167	1			T5	5		T12	1		T16	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T31	12		T205	1		T183	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T13	1		T36	2		T165	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T132	3		T21	3		T136	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T7	8		T8	2		T221	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T60	3		T138	1		T226	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T84	1		T204	5		T243	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T39	2		T167	12		T256	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14014	1			T1	20		T2	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T143	1		T148	8		T189	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T42	7		T134	10		T138	24
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T59	7		T137	15		T222	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T84	12		T165	11		T88	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T14	7		T41	12		T132	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T60	10		T179	11		T232	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T35	1		T84	13		T133	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T10	7		T42	19		T129	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T234	15		T228	3		T246	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T140	15		T247	16		T248	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T242	6		T32	7		T246	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T244	12		T249	13		T248	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T59	8		T166	13		T244	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1253	1			T12	11		T16	44		T171	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T183	1		T143	17		T145	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T13	17		T165	10		T237	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T132	2		T21	1		T222	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	3		T8	1		T221	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T60	11		T138	5		T226	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T84	15		T312	12		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T39	1		T167	13		T188	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T230	2		T227	12		T219	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T143	16		T189	11		T306	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T84	1		T166	1		T271	17
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T226	1		T256	1		T32	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T313	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T193	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T135	8		T134	1		T138	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T59	3		T137	16		T222	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T17	1		T42	1		T84	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T14	7		T34	11		T41	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T60	12		T50	1		T172	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T35	4		T84	1		T59	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T10	9		T42	1		T133	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T224	2		T223	1		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T82	8		T136	5		T129	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T15	13		T201	1		T224	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T220	1		T140	1		T249	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T200	1		T141	1		T139	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T41	2		T220	1		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T31	12		T59	13		T205	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T13	1		T34	1		T36	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T132	3		T136	9		T222	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1217	1			T5	5		T7	8		T8	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T21	3		T60	3		T138	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13965	1			T1	20		T2	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T84	15		T166	16		T271	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T226	16		T258	16		T238	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T193	19		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T134	10		T138	24		T151	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T59	7		T137	15		T222	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T42	7		T84	12		T165	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T14	7		T41	12		T132	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T60	10		T179	11		T232	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T35	1		T84	13		T59	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T10	7		T42	19		T133	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T234	15		T233	4		T96	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T129	16		T248	7		T219	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T242	6		T32	7		T228	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T140	15		T249	13		T247	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T244	10		T236	12		T167	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T225	7		T244	12		T253	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T59	8		T166	13		T207	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T13	17		T165	10		T253	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T132	2		T222	13		T142	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1292	1			T7	3		T8	1		T12	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T21	1		T60	11		T138	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18481

1

T1

20

T2

20

T4

20

auto[1]

auto[0]

4153

1

T7

3

T8

1

T10

7