Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22634

1

T1

20

T2

20

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19216

1

T1

20

T2

20

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3418

1

T8

3

T10

16

T14

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16780

1

T1

20

T2

20

T4

20

auto[1]

5854

1

T5

5

T10

16

T12

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18984

1

T1

20

T2

20

T4

20

auto[1]

3650

1

T5

4

T7

3

T8

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	179	1			T133	13		T138	10		T249	14
values[0]	43	1			T13	18		T309	5		T240	19
values[1]	718	1			T221	7		T132	23		T136	9
values[2]	2927	1			T5	5		T12	12		T16	47
values[3]	495	1			T10	16		T14	14		T34	1
values[4]	686	1			T41	25		T31	12		T191	34
values[5]	561	1			T41	2		T35	5		T200	1
values[6]	477	1			T7	11		T17	1		T201	1
values[7]	614	1			T135	8		T136	5		T224	2
values[8]	794	1			T8	3		T42	8		T59	19
values[9]	1175	1			T15	13		T84	27		T36	2
minimum	13965	1			T1	20		T2	20		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	699	1			T221	7		T136	9		T141	1
values[1]	2787	1			T5	5		T10	16		T12	12
values[2]	592	1			T14	14		T34	1		T82	8
values[3]	777	1			T41	25		T31	12		T140	4
values[4]	458	1			T41	2		T35	5		T200	1
values[5]	491	1			T7	11		T17	1		T136	5
values[6]	635	1			T135	8		T224	2		T160	12
values[7]	818	1			T8	3		T42	8		T59	19
values[8]	1078	1			T15	13		T84	27		T36	2
values[9]	83	1			T32	30		T311	9		T218	2
minimum	14216	1			T1	20		T2	20		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18481

1

T1

20

T2

20

T4

20

auto[1]

4153

1

T7

3

T8

1

T10

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T136	1		T205	1		T166	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T221	4		T141	1		T133	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1611	1			T5	1		T12	12		T16	47
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T10	8		T34	1		T42	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T82	1		T59	8		T220	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T14	8		T34	1		T201	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T41	13		T140	1		T50	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T31	1		T140	3		T50	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T35	5		T201	1		T59	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T41	1		T200	1		T255	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T7	8		T136	1		T166	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T17	1		T223	1		T138	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T165	12		T231	1		T196	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T135	1		T224	1		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T59	10		T133	7		T151	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T8	2		T42	8		T137	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T133	7		T60	11		T38	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	360	1			T15	1		T84	27		T36	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T32	16		T310	2		T330	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T311	1		T218	1		T312	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13932	1			T1	20		T2	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T165	1		T257	1		T248	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T136	8		T266	14		T277	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T221	3		T38	3		T225	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	909	1			T5	4		T83	10		T259	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T10	8		T34	10		T237	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T82	7		T59	2		T230	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T14	6		T224	9		T60	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T41	12		T50	12		T232	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T31	11		T244	12		T192	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T59	12		T165	7		T302	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T41	1		T147	10		T289	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T7	3		T136	4		T314	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T237	10		T281	6		T278	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T165	12		T231	12		T227	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T135	7		T224	1		T160	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T59	9		T133	7		T151	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T8	1		T137	15		T129	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T133	6		T60	11		T139	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T15	12		T132	2		T139	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T32	14		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T311	8		T218	1		T312	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T36	2		T132	9		T38	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T165	1		T248	9		T245	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T133	7		T236	13		T242	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T138	10		T249	14		T167	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T13	18		T309	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T240	10		T313	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T132	14		T136	1		T205	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T221	4		T133	9		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1666	1			T5	1		T12	12		T16	47
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T34	1		T84	16		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T82	1		T59	8		T21	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T10	8		T14	8		T34	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T41	13		T140	1		T50	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T31	1		T191	16		T140	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T35	5		T59	9		T172	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T41	1		T200	1		T244	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T7	8		T201	1		T165	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T17	1		T223	1		T138	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T136	1		T165	12		T196	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T135	1		T224	1		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T59	10		T133	7		T151	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T8	2		T42	8		T137	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T60	11		T38	1		T222	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	379	1			T15	1		T84	27		T36	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13867	1			T1	20		T2	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T133	6		T236	14		T242	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T167	11		T312	9		T239	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T309	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T240	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T132	9		T136	8		T183	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T221	3		T165	1		T225	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	945	1			T5	4		T83	10		T259	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T34	10		T38	3		T179	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T82	7		T59	2		T230	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T10	8		T14	6		T224	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T41	12		T50	12		T235	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T31	11		T191	18		T207	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T59	12		T232	15		T167	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T41	1		T244	12		T289	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T7	3		T165	7		T314	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T237	10		T281	6		T278	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T136	4		T165	12		T227	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T135	7		T224	1		T160	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T59	9		T133	7		T151	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T8	1		T137	15		T129	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T60	11		T139	13		T244	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T15	12		T132	2		T139	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T36	2		T38	1		T130	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T136	9		T205	1		T166	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T221	4		T141	1		T133	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1226	1			T5	5		T12	1		T16	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T10	9		T34	11		T42	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T82	8		T59	3		T220	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T14	7		T34	1		T201	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T41	13		T140	1		T50	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T31	12		T140	1		T50	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T35	4		T201	1		T59	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T41	2		T200	1		T255	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T7	8		T136	5		T166	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T17	1		T223	1		T138	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T165	13		T231	13		T196	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T135	8		T224	2		T160	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T59	10		T133	8		T151	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T8	2		T42	1		T137	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T133	7		T60	12		T38	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T15	13		T84	2		T36	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T32	15		T310	2		T330	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T311	9		T218	2		T312	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14026	1			T1	20		T2	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T165	2		T257	1		T248	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T166	13		T266	8		T145	21
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T221	3		T133	8		T38	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T12	11		T16	44		T171	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T10	7		T42	19		T84	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T59	7		T230	2		T271	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T14	7		T191	15		T142	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T41	12		T232	4		T247	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T140	2		T244	12		T197	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T35	1		T59	8		T165	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T147	11		T289	3		T315	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T7	3		T166	17		T197	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T138	20		T140	15		T237	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T165	11		T227	6		T298	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T39	1		T50	15		T249	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T59	9		T133	6		T151	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T8	1		T42	7		T137	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T133	6		T60	10		T222	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T84	25		T132	2		T138	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T32	15		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T312	2		T317	1		T345	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T13	17		T132	13		T183	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T248	8		T219	14		T245	17

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T133	7		T236	15		T242	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T138	1		T249	1		T167	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T13	1		T309	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T240	10		T313	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T132	10		T136	9		T205	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T221	4		T133	1		T165	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1267	1			T5	5		T12	1		T16	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T34	11		T84	1		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T82	8		T59	3		T21	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T10	9		T14	7		T34	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T41	13		T140	1		T50	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T31	12		T191	19		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T35	4		T59	13		T172	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T41	2		T200	1		T244	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T7	8		T201	1		T165	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T17	1		T223	1		T138	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T136	5		T165	13		T196	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T135	8		T224	2		T160	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T59	10		T133	8		T151	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T8	2		T42	1		T137	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T60	12		T38	1		T222	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T15	13		T84	2		T36	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13965	1			T1	20		T2	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T133	6		T236	12		T242	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T138	9		T249	13		T167	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T13	17		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T240	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T132	13		T183	1		T166	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T221	3		T133	8		T225	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1344	1			T12	11		T16	44		T171	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T84	15		T134	10		T38	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T59	7		T21	1		T230	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T10	7		T14	7		T42	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T41	12		T247	8		T248	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T191	15		T140	2		T207	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T35	1		T59	8		T232	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T244	12		T289	3		T315	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T7	3		T165	10		T166	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T138	20		T237	8		T147	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T165	11		T227	6		T298	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T140	15		T50	15		T244	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T59	9		T133	6		T151	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T8	1		T42	7		T137	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T60	10		T222	13		T244	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T84	25		T132	2		T222	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18481

1

T1

20

T2

20

T4

20

auto[1]

auto[0]

4153

1

T7

3

T8

1

T10

7