Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T177	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T228	1		T264	3		T265	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T148	1		T254	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T42	8		T59	9		T133	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T41	13		T21	4		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T34	1		T60	12		T165	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T34	1		T224	1		T222	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T36	2		T135	1		T223	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T14	8		T84	13		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T17	1		T59	8		T205	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T7	8		T35	5		T137	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1650	1			T5	1		T12	12		T16	47
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T200	1		T132	3		T237	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T10	8		T15	1		T201	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T13	18		T42	20		T221	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T140	1		T142	14		T256	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T82	1		T59	10		T233	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T172	1		T227	5		T197	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T255	1		T143	15		T192	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T41	1		T31	1		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	408	1			T8	2		T84	14		T201	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13867	1			T1	20		T2	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T177	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T264	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T148	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T59	12		T139	3		T50	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T41	12		T129	16		T151	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T34	10		T60	2		T165	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T224	1		T39	1		T139	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T135	7		T160	11		T225	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T14	6		T224	9		T142	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T59	2		T234	11		T266	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T7	3		T137	15		T60	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	917	1			T5	4		T83	10		T259	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T132	2		T237	7		T227	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T10	8		T15	12		T165	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T221	3		T132	9		T207	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T142	11		T29	1		T218	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T82	7		T59	9		T233	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T227	13		T229	6		T267	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T192	5		T148	22		T154	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T41	1		T31	11		T136	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T8	1		T136	4		T38	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T36	2		T38	1		T130	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T42	1		T59	13		T133	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T141	1		T129	17		T151	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T34	11		T36	2		T135	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T34	1		T84	1		T21	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T223	1		T166	1		T234	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T14	7		T137	16		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1214	1			T5	5		T12	1		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T7	8		T35	4		T200	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T15	13		T138	2		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T221	4		T132	13		T237	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T10	9		T84	1		T60	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T13	1		T42	1		T220	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T201	1		T256	1		T29	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T82	8		T59	10		T233	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T41	2		T133	7		T172	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T8	2		T38	6		T255	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T136	9		T133	8		T191	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T84	1		T136	5		T223	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T31	12		T248	10		T144	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T201	1		T138	1		T257	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13965	1			T1	20		T2	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T41	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T42	7		T59	8		T133	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T129	16		T151	4		T222	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T60	11		T165	10		T225	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T84	12		T21	1		T140	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T166	13		T234	13		T258	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T14	7		T137	15		T60	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1238	1			T12	11		T16	44		T171	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	3		T35	1		T140	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T138	20		T145	9		T219	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T221	3		T132	15		T237	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T10	7		T84	15		T142	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T13	17		T42	19		T226	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T29	1		T261	11		T268	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T59	9		T233	4		T143	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T133	6		T227	16		T197	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T8	1		T38	3		T249	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T133	6		T191	15		T242	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T84	13		T50	15		T244	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T248	8		T144	8		T269	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T138	9		T25	1		T174	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T41	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T177	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T228	1		T264	5		T265	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T148	8		T254	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T42	1		T59	13		T133	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T41	13		T21	3		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T34	11		T60	3		T165	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T34	1		T224	2		T222	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T36	2		T135	8		T223	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T14	7		T84	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T17	1		T59	3		T205	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	8		T35	4		T137	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1246	1			T5	5		T12	1		T16	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T200	1		T132	3		T237	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T10	9		T15	13		T201	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T13	1		T42	1		T221	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T140	1		T142	12		T256	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T82	8		T59	10		T233	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T172	1		T227	14		T197	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T255	1		T143	1		T192	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	334	1			T41	2		T31	12		T136	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	381	1			T8	2		T84	1		T201	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13965	1			T1	20		T2	20		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T264	2		T265	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T42	7		T59	8		T133	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T41	12		T21	1		T129	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T60	11		T165	10		T226	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T222	5		T39	1		T140	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T225	7		T166	13		T270	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T14	7		T84	12		T142	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T59	7		T234	13		T266	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T7	3		T35	1		T137	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1321	1			T12	11		T16	44		T84	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T132	2		T237	7		T227	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T10	7		T166	16		T244	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T13	17		T42	19		T221	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T142	13		T219	25		T29	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T59	9		T233	4		T143	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T227	4		T197	4		T229	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T143	14		T192	4		T148	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T133	12		T191	15		T227	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T8	1		T84	13		T138	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18481

1

T1

20

T2

20

T4

20

auto[1]

auto[0]

4153

1

T7

3

T8

1

T10

7