Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22634

1

T1

20

T2

20

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19187

1

T1

20

T2

20

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3447

1

T8

3

T15

13

T17

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16708

1

T1

20

T2

20

T4

20

auto[1]

5926

1

T5

5

T7

14

T8

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18984

1

T1

20

T2

20

T4

20

auto[1]

3650

1

T5

4

T7

3

T8

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	525	1			T7	3		T35	2		T36	8
values[0]	1	1			T299	1		-	-		-	-
values[1]	593	1			T14	14		T141	1		T133	14
values[2]	2783	1			T5	5		T10	16		T12	12
values[3]	857	1			T34	12		T141	1		T129	33
values[4]	512	1			T17	1		T35	5		T31	12
values[5]	832	1			T42	20		T132	23		T135	8
values[6]	543	1			T7	11		T200	1		T201	1
values[7]	546	1			T15	13		T42	8		T59	21
values[8]	711	1			T82	8		T84	13		T221	7
values[9]	1034	1			T8	3		T13	18		T41	25
minimum	13697	1			T1	20		T2	20		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	567	1			T14	14		T133	14		T224	10
values[1]	2817	1			T5	5		T10	16		T12	12
values[2]	829	1			T34	12		T141	1		T129	33
values[3]	581	1			T17	1		T35	5		T31	12
values[4]	715	1			T42	20		T135	8		T137	31
values[5]	628	1			T7	11		T15	13		T200	1
values[6]	539	1			T42	8		T59	21		T136	5
values[7]	771	1			T41	25		T82	8		T84	27
values[8]	879	1			T8	3		T59	10		T60	22
values[9]	211	1			T13	18		T225	14		T139	1
minimum	14097	1			T1	20		T2	20		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18481

1

T1

20

T2

20

T4

20

auto[1]

4153

1

T7

3

T8

1

T10

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T14	8		T160	1		T50	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T133	7		T224	1		T60	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1540	1			T5	1		T10	8		T12	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T201	1		T36	2		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T34	2		T129	17		T138	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T141	1		T223	1		T138	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T84	16		T132	14		T172	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T17	1		T35	5		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T137	16		T60	1		T151	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T42	20		T135	1		T222	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T7	8		T200	1		T201	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T15	1		T21	4		T133	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T136	1		T220	1		T257	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T42	8		T59	9		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T221	4		T132	3		T165	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T41	13		T82	1		T84	27
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T59	8		T138	10		T226	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T8	2		T60	11		T38	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T13	18		T225	8		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T142	10		T300	1		T301	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13917	1			T1	20		T2	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T244	5		T227	13		T192	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T14	6		T160	11		T234	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T133	7		T224	9		T60	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	875	1			T5	4		T10	8		T41	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T191	18		T237	7		T167	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T34	10		T129	16		T142	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T230	2		T192	5		T153	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T132	9		T227	13		T302	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T31	11		T244	12		T236	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T137	15		T60	1		T151	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T135	7		T225	5		T50	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T7	3		T277	9		T148	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T15	12		T133	6		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T136	4		T266	11		T248	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T59	12		T139	13		T234	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T221	3		T132	2		T165	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T41	12		T82	7		T59	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T59	2		T226	8		T236	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T8	1		T60	11		T38	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T225	6		T303	19		T176	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T142	9		T300	15		T301	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T36	2		T38	1		T130	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T244	6		T227	10		T192	15

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	340	1			T7	3		T35	2		T36	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T142	10		T183	6		T196	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T299	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T14	8		T141	1		T160	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T133	7		T224	1		T60	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1530	1			T5	1		T10	8		T12	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T201	1		T36	2		T191	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T34	2		T129	17		T138	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T141	1		T138	16		T38	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T84	16		T172	1		T251	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T17	1		T35	5		T31	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T132	14		T137	16		T151	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T42	20		T135	1		T222	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T7	8		T200	1		T201	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T21	4		T39	2		T140	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T136	1		T223	1		T220	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T15	1		T42	8		T59	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T221	4		T132	3		T222	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T82	1		T84	13		T59	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T13	18		T59	8		T138	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T8	2		T41	13		T84	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13599	1			T1	20		T2	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T226	8		T236	12		T304	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T142	9		T183	1		T227	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T14	6		T160	11		T234	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T133	7		T224	9		T60	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	861	1			T5	4		T10	8		T41	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T191	18		T237	7		T167	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T34	10		T129	16		T32	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T153	12		T305	14		T258	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T88	2		T148	22		T241	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T31	11		T244	12		T230	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T132	9		T137	15		T151	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T135	7		T225	5		T50	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T7	3		T60	1		T167	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T39	1		T32	14		T271	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T136	4		T266	3		T248	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T15	12		T59	12		T133	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T221	3		T132	2		T139	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T82	7		T59	9		T224	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T59	2		T165	7		T225	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T8	1		T41	12		T60	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T36	2		T38	1		T130	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T14	7		T160	12		T50	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T133	8		T224	10		T60	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1191	1			T5	5		T10	9		T12	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T201	1		T36	2		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T34	12		T129	17		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T141	1		T223	1		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T84	1		T132	10		T172	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T17	1		T35	4		T31	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T137	16		T60	2		T151	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T42	1		T135	8		T222	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T7	8		T200	1		T201	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T15	13		T21	3		T133	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T136	5		T220	1		T257	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T42	1		T59	13		T139	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T221	4		T132	3		T165	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T41	13		T82	8		T84	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T59	3		T138	1		T226	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T8	2		T60	12		T38	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T13	1		T225	7		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T142	10		T300	16		T301	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13976	1			T1	20		T2	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T244	7		T227	11		T192	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T14	7		T234	15		T233	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T133	6		T60	11		T165	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1224	1			T10	7		T12	11		T16	44
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T191	15		T166	17		T237	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T129	16		T138	5		T142	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T138	15		T230	2		T253	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T84	15		T132	13		T251	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T35	1		T244	10		T236	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T137	15		T151	4		T167	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T42	19		T222	5		T50	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T7	3		T134	10		T166	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T21	1		T133	6		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T249	13		T266	6		T248	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T42	7		T59	8		T234	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T221	3		T132	2		T165	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T41	12		T84	25		T59	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T59	7		T138	9		T226	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T8	1		T60	10		T38	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T13	17		T225	7		T92	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T142	9		T301	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T270	22		T193	7		T306	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T244	4		T227	12		T192	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	336	1			T7	3		T35	2		T36	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T142	10		T183	6		T196	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T299	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T14	7		T141	1		T160	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T133	8		T224	10		T60	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1177	1			T5	5		T10	9		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T201	1		T36	2		T191	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T34	12		T129	17		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T141	1		T138	1		T38	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T84	1		T172	1		T251	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T17	1		T35	4		T31	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T132	10		T137	16		T151	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T42	1		T135	8		T222	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T7	8		T200	1		T201	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T21	3		T39	2		T140	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T136	5		T223	1		T220	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T15	13		T42	1		T59	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T221	4		T132	3		T222	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T82	8		T84	1		T59	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T13	1		T59	3		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T8	2		T41	13		T84	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13697	1			T1	20		T2	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T226	8		T304	8		T303	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T142	9		T183	1		T227	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T14	7		T234	15		T233	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T133	6		T60	11		T165	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1214	1			T10	7		T12	11		T16	44
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T191	15		T166	17		T237	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T129	16		T138	5		T166	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T138	15		T249	13		T253	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T84	15		T251	13		T88	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T35	1		T244	10		T230	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T132	13		T137	15		T151	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T42	19		T222	5		T50	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T7	3		T134	10		T166	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T21	1		T39	1		T140	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T266	2		T248	8		T307	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T42	7		T59	8		T133	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T221	3		T132	2		T222	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T84	12		T59	9		T133	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T13	17		T59	7		T138	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T8	1		T41	12		T84	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18481

1

T1

20

T2

20

T4

20

auto[1]

auto[0]

4153

1

T7

3

T8

1

T10

7