Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22634

1

T1

20

T2

20

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19445

1

T1

20

T2

20

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3189

1

T8

3

T10

16

T13

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16373

1

T1

20

T2

20

T4

20

auto[1]

6261

1

T5

5

T7

11

T8

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18984

1

T1

20

T2

20

T4

20

auto[1]

3650

1

T5

4

T7

3

T8

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	214	1			T42	20		T223	1		T151	9
values[0]	9	1			T173	7		T97	1		T319	1
values[1]	601	1			T35	5		T31	12		T224	2
values[2]	669	1			T13	18		T133	14		T60	22
values[3]	838	1			T14	14		T84	16		T200	1
values[4]	890	1			T34	11		T41	2		T84	14
values[5]	2792	1			T5	5		T12	12		T16	47
values[6]	512	1			T7	11		T41	25		T82	8
values[7]	666	1			T10	16		T42	8		T84	13
values[8]	619	1			T8	3		T136	9		T137	31
values[9]	859	1			T15	13		T17	1		T34	1
minimum	13965	1			T1	20		T2	20		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	476	1			T13	18		T35	5		T31	12
values[1]	705	1			T84	16		T133	14		T134	11
values[2]	971	1			T14	14		T200	1		T201	1
values[3]	2913	1			T5	5		T12	12		T16	47
values[4]	657	1			T7	11		T21	4		T60	14
values[5]	449	1			T41	25		T82	8		T201	1
values[6]	724	1			T10	16		T42	8		T84	13
values[7]	625	1			T8	3		T221	7		T132	5
values[8]	774	1			T15	13		T34	1		T42	20
values[9]	145	1			T17	1		T138	16		T314	16
minimum	14195	1			T1	20		T2	20		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18481

1

T1

20

T2

20

T4

20

auto[1]

4153

1

T7

3

T8

1

T10

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T224	1		T38	1		T172	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T13	18		T35	5		T31	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T84	16		T134	11		T222	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T133	7		T257	1		T227	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T14	8		T200	1		T132	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T201	1		T165	11		T225	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1514	1			T5	1		T12	12		T16	47
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T84	14		T36	2		T59	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	8		T60	12		T138	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T21	4		T281	1		T235	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T82	1		T201	1		T320	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T41	13		T60	1		T88	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T42	8		T59	8		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T10	8		T84	13		T59	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T165	1		T50	1		T166	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T8	2		T221	4		T132	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T42	20		T141	1		T151	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T15	1		T34	1		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T314	1		T219	15		T90	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T17	1		T138	16		T92	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13954	1			T1	20		T2	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T223	1		T160	1		T39	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T224	1		T233	10		T321	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T31	11		T60	11		T248	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T234	11		T227	6		T144	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T133	7		T227	10		T236	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T14	6		T132	9		T226	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T165	7		T225	5		T179	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	869	1			T5	4		T34	10		T41	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T59	12		T224	9		T165	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T7	3		T60	2		T38	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T281	6		T235	11		T192	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T82	7		T320	13		T278	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T41	12		T60	1		T88	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T59	2		T135	7		T129	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T10	8		T59	9		T136	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T165	1		T207	7		T168	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T8	1		T221	3		T132	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T151	4		T153	12		T305	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T15	12		T136	4		T139	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T314	15		T154	12		T240	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T315	4		T322	1		T323	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T36	2		T38	1		T130	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T160	11		T39	1		T231	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T42	20		T151	5		T166	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T223	1		T275	1		T92	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T173	7		T97	1		T319	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T224	1		T38	1		T172	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T35	5		T31	1		T223	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T134	11		T222	6		T234	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T13	18		T133	7		T60	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T14	8		T84	16		T200	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T201	1		T165	11		T257	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T34	1		T41	1		T138	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T84	14		T36	2		T59	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1563	1			T5	1		T12	12		T16	47
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T21	4		T224	1		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T7	8		T82	1		T201	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T41	13		T281	1		T204	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T42	8		T59	8		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T10	8		T84	13		T132	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T165	1		T166	17		T143	32
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T8	2		T136	1		T137	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T141	1		T50	1		T251	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T15	1		T17	1		T34	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13867	1			T1	20		T2	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T151	4		T305	11		T148	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T322	1		T323	9		T324	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T224	1		T233	10		T236	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T31	11		T160	11		T39	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T234	11		T167	11		T144	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T133	7		T60	11		T227	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T14	6		T132	9		T226	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T165	7		T179	9		T234	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T34	10		T41	1		T191	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T59	12		T165	12		T225	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	920	1			T5	4		T83	10		T259	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T224	9		T235	11		T192	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	3		T82	7		T320	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T41	12		T281	6		T147	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T59	2		T135	7		T129	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T10	8		T132	2		T59	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T165	1		T315	2		T325	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T8	1		T136	8		T137	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T314	15		T153	12		T148	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T15	12		T221	3		T136	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T36	2		T38	1		T130	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T224	2		T38	1		T172	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T13	1		T35	4		T31	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T84	1		T134	1		T222	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T133	8		T257	1		T227	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T14	7		T200	1		T132	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T201	1		T165	8		T225	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1187	1			T5	5		T12	1		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T84	1		T36	2		T59	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T7	8		T60	3		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T21	3		T281	7		T235	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T82	8		T201	1		T320	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T41	13		T60	2		T88	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T42	1		T59	3		T135	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T10	9		T84	1		T59	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T165	2		T50	1		T166	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T8	2		T221	4		T132	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T42	1		T141	1		T151	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T15	13		T34	1		T136	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T314	16		T219	1		T90	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T17	1		T138	1		T92	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14022	1			T1	20		T2	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T223	1		T160	12		T39	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T233	4		T249	13		T253	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T13	17		T35	1		T60	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T84	15		T134	10		T222	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T133	6		T227	12		T91	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T14	7		T132	13		T226	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T165	10		T179	11		T237	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1196	1			T12	11		T16	44		T171	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T84	13		T59	8		T165	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T7	3		T60	11		T138	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T21	1		T197	17		T192	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T283	5		T258	16		T326	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T41	12		T88	8		T252	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T42	7		T59	7		T129	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T10	7		T84	12		T59	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T166	16		T207	4		T143	30
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T8	1		T221	3		T132	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T42	19		T151	4		T166	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T183	1		T244	16		T237	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T219	14		T90	5		T240	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T138	15		T92	6		T315	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T236	12		T246	6		T173	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T39	1		T266	2		T188	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T42	1		T151	5		T166	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T223	1		T275	1		T92	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T173	1		T97	1		T319	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T224	2		T38	1		T172	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T35	4		T31	12		T223	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T134	1		T222	1		T234	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	1		T133	8		T60	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T14	7		T84	1		T200	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T201	1		T165	8		T257	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T34	11		T41	2		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T84	1		T36	2		T59	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1246	1			T5	5		T12	1		T16	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T21	3		T224	10		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T7	8		T82	8		T201	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T41	13		T281	7		T204	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T42	1		T59	3		T135	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T10	9		T84	1		T132	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T165	2		T166	1		T143	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T8	2		T136	9		T137	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T141	1		T50	1		T251	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T15	13		T17	1		T34	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13965	1			T1	20		T2	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T42	19		T151	4		T166	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T92	6		T268	14		T323	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T173	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T233	4		T249	13		T236	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T35	1		T39	1		T266	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T134	10		T222	5		T234	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T13	17		T133	6		T60	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T14	7		T84	15		T132	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T165	10		T179	11		T234	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T138	9		T191	15		T143	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T84	13		T59	8		T165	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1237	1			T12	11		T16	44		T171	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T21	1		T197	17		T192	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T7	3		T307	9		T258	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T41	12		T252	10		T238	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T42	7		T59	7		T129	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T10	7		T84	12		T132	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T166	16		T143	30		T173	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T8	1		T137	15		T133	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T251	13		T228	18		T90	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T221	3		T138	15		T226	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18481

1

T1

20

T2

20

T4

20

auto[1]

auto[0]

4153

1

T7

3

T8

1

T10

7