Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22634

1

T1

20

T2

20

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19261

1

T1

20

T2

20

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3373

1

T7

11

T8

3

T10

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17373

1

T1

20

T2

20

T4

20

auto[1]

5261

1

T5

5

T8

3

T12

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18984

1

T1

20

T2

20

T4

20

auto[1]

3650

1

T5

4

T7

3

T8

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	68	1			T132	5		T225	14		T98	32
values[0]	46	1			T231	1		T277	10		T169	9
values[1]	705	1			T201	1		T135	8		T60	22
values[2]	686	1			T42	20		T59	10		T60	14
values[3]	574	1			T221	7		T141	1		T133	9
values[4]	2836	1			T5	5		T10	16		T12	12
values[5]	557	1			T7	11		T35	5		T42	8
values[6]	598	1			T38	9		T165	2		T39	3
values[7]	697	1			T8	3		T14	14		T15	13
values[8]	744	1			T59	21		T136	9		T137	31
values[9]	1158	1			T13	18		T34	1		T41	27
minimum	13965	1			T1	20		T2	20		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	989	1			T42	20		T201	1		T135	8
values[1]	624	1			T59	10		T141	1		T133	9
values[2]	637	1			T10	16		T221	7		T224	10
values[3]	2804	1			T5	5		T7	11		T12	12
values[4]	403	1			T35	5		T42	8		T201	1
values[5]	626	1			T14	14		T31	12		T200	1
values[6]	881	1			T8	3		T15	13		T17	1
values[7]	631	1			T41	25		T82	8		T136	9
values[8]	995	1			T13	18		T34	1		T41	2
values[9]	78	1			T133	13		T50	30		T275	1
minimum	13966	1			T1	20		T2	20		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18481

1

T1

20

T2

20

T4

20

auto[1]

4153

1

T7

3

T8

1

T10

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9] , minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T135	1		T60	12		T40	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T42	20		T201	1		T165	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T141	1		T133	9		T138	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T59	8		T60	11		T165	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T224	1		T130	1		T276	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T10	8		T221	4		T222	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1563	1			T5	1		T12	12		T16	47
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T7	8		T84	14		T132	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T35	5		T42	8		T226	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T201	1		T138	16		T38	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T136	1		T140	16		T142	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T14	8		T31	1		T200	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T17	1		T34	1		T59	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T8	2		T15	1		T223	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T41	13		T136	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T82	1		T134	11		T226	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T34	1		T84	29		T36	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T13	18		T41	1		T224	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T133	7		T50	16		T197	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T275	1		T330	1		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13867	1			T1	20		T2	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T331	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T135	7		T60	2		T277	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T165	12		T234	16		T88	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T160	11		T183	1		T25	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T59	2		T60	11		T165	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T224	9		T320	13		T145	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T10	8		T221	3		T225	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	869	1			T5	4		T83	10		T259	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T7	3		T132	9		T129	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T241	9		T280	2		T218	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T38	3		T244	12		T234	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T136	4		T142	9		T50	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T14	6		T31	11		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T34	10		T59	12		T137	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T8	1		T15	12		T165	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T41	12		T136	8		T139	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T82	7		T226	8		T207	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T132	2		T59	9		T231	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T41	1		T224	1		T60	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T133	6		T50	14		T284	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T36	2		T38	1		T130	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T132	3		T304	9		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T225	8		T98	21		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T231	1		T277	1		T169	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T331	1		T332	1		T294	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T135	1		T138	6		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T201	1		T60	11		T166	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T60	12		T160	1		T183	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T42	20		T59	8		T165	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T141	1		T133	9		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T221	4		T222	14		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1599	1			T5	1		T12	12		T16	47
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T10	8		T84	14		T21	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T35	5		T42	8		T23	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T7	8		T201	1		T132	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T226	17		T140	16		T142	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T38	6		T165	1		T39	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T17	1		T34	1		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T8	2		T14	8		T15	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T59	9		T136	1		T137	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T134	11		T138	10		T226	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	421	1			T34	1		T41	13		T84	29
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T13	18		T41	1		T82	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13867	1			T1	20		T2	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T132	2		T304	8		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T225	6		T98	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T277	9		T333	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T239	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T135	7		T283	12		T147	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T60	11		T227	6		T88	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T60	2		T160	11		T183	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T59	2		T165	19		T244	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T320	13		T153	12		T307	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T221	3		T225	5		T314	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	886	1			T5	4		T83	10		T259	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T10	8		T129	16		T167	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T305	14		T218	14		T199	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T7	3		T132	9		T244	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T142	9		T244	12		T229	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T38	3		T165	1		T39	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T34	10		T136	4		T133	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T8	1		T14	6		T15	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T59	12		T136	8		T137	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T226	8		T207	7		T235	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T41	12		T59	9		T133	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T41	1		T82	7		T224	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T36	2		T38	1		T130	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T135	8		T60	3		T40	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T42	1		T201	1		T165	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T141	1		T133	1		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T59	3		T60	12		T165	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T224	10		T130	1		T276	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T10	9		T221	4		T222	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1187	1			T5	5		T12	1		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T7	8		T84	1		T132	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T35	4		T42	1		T226	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T201	1		T138	1		T38	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T136	5		T140	1		T142	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T14	7		T31	12		T200	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T17	1		T34	11		T59	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T8	2		T15	13		T223	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T41	13		T136	9		T139	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T82	8		T134	1		T226	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T34	1		T84	2		T36	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T13	1		T41	2		T224	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T133	7		T50	15		T197	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T275	1		T330	1		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13965	1			T1	20		T2	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T331	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T60	11		T143	33		T283	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T42	19		T165	11		T166	46
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T133	8		T138	5		T183	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T59	7		T60	10		T165	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T145	9		T307	9		T315	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T10	7		T221	3		T222	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1245	1			T12	11		T16	44		T171	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	3		T84	13		T132	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T35	1		T42	7		T226	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T138	15		T38	3		T244	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T140	15		T142	9		T244	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T14	7		T39	1		T232	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T59	8		T137	15		T133	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T8	1		T138	9		T237	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T41	12		T179	11		T249	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T134	10		T226	8		T140	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T84	27		T132	2		T59	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T13	17		T151	4		T225	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T133	6		T50	15		T197	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T132	3		T304	9		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T225	7		T98	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T231	1		T277	10		T169	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T331	1		T332	1		T294	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T135	8		T138	1		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T201	1		T60	12		T166	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T60	3		T160	12		T183	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T42	1		T59	3		T165	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T141	1		T133	1		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T221	4		T222	1		T225	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1210	1			T5	5		T12	1		T16	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T10	9		T84	1		T21	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T35	4		T42	1		T23	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T7	8		T201	1		T132	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T226	1		T140	1		T142	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T38	6		T165	2		T39	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T17	1		T34	11		T136	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T8	2		T14	7		T15	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T59	13		T136	9		T137	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T134	1		T138	1		T226	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	349	1			T34	1		T41	13		T84	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T13	1		T41	2		T82	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13965	1			T1	20		T2	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T132	2		T304	8		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T225	7		T98	20		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T169	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T294	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T138	5		T283	5		T271	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T60	10		T166	16		T227	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T60	11		T183	1		T143	33
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T42	19		T59	7		T165	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T133	8		T307	9		T252	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T221	3		T222	13		T252	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1275	1			T12	11		T16	44		T171	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T10	7		T84	13		T21	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T35	1		T42	7		T326	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T7	3		T132	13		T138	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T226	16		T140	15		T142	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T38	3		T39	1		T247	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T133	6		T191	15		T249	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T8	1		T14	7		T232	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T59	8		T137	15		T227	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T134	10		T138	9		T226	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	356	1			T41	12		T84	27		T59	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T13	17		T151	4		T143	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18481

1

T1

20

T2

20

T4

20

auto[1]

auto[0]

4153

1

T7

3

T8

1

T10

7