Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	5395	1			T3	9		T4	6		T5	3
testmodes[AdcCtrlTestmodeNormal]	4562	1			T3	10		T4	7		T5	8
testmodes[AdcCtrlTestmodeLowpower]	4698	1			T6	3		T10	1		T12	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	2805	1			T3	3		T4	2		T5	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1381	1			T3	5		T4	3		T5	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1099	1			T13	2		T38	10		T77	13
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1389	1			T3	5		T4	3		T5	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1683	1			T3	5		T4	4		T5	5
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1145	1			T10	1		T13	2		T14	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1093	1			T13	1		T69	1		T70	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1149	1			T6	1		T10	1		T12	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2212	1			T6	2		T12	2		T13	3