Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.70 99.07 96.67 100.00 100.00 98.83 98.33 91.02


Total tests in report: 919
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
64.74 64.74 96.85 96.85 78.10 78.10 64.93 64.93 24.32 24.32 95.18 95.18 86.64 86.64 7.16 7.16 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_clock_gating.1681629252
80.52 15.78 98.67 1.82 88.10 10.00 96.45 31.52 67.57 43.24 98.21 3.03 89.65 3.01 25.01 17.84 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3749596230
83.71 3.19 98.83 0.15 92.96 4.86 97.16 0.71 75.68 8.11 98.33 0.12 90.98 1.34 32.04 7.04 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_both.1615255271
85.79 2.08 98.83 0.00 93.00 0.04 97.16 0.00 89.19 13.51 98.39 0.06 90.98 0.00 32.99 0.95 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.2802593375
87.06 1.27 98.83 0.00 93.25 0.25 97.16 0.00 89.19 0.00 98.39 0.00 91.32 0.33 41.30 8.31 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_both.1089378799
88.27 1.21 98.83 0.00 93.25 0.00 97.16 0.00 91.89 2.70 98.39 0.00 95.33 4.01 43.07 1.77 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.2259320311
89.44 1.17 98.89 0.06 93.78 0.54 97.16 0.00 97.30 5.41 98.45 0.06 95.33 0.00 45.17 2.10 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1725305722
90.46 1.02 98.89 0.00 93.87 0.08 97.16 0.00 97.30 0.00 98.45 0.00 95.49 0.17 52.08 6.91 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_clock_gating.759495862
91.23 0.77 98.89 0.00 93.87 0.00 97.16 0.00 97.30 0.00 98.45 0.00 95.66 0.17 57.30 5.22 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_clock_gating.247944245
91.77 0.53 98.89 0.00 93.87 0.00 97.16 0.00 97.30 0.00 98.45 0.00 95.66 0.00 61.04 3.74 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_both.399313051
92.23 0.46 98.89 0.00 95.27 1.40 97.63 0.47 97.30 0.00 98.52 0.06 96.33 0.67 61.69 0.65 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.237000460
92.67 0.44 98.89 0.00 95.27 0.00 97.63 0.00 100.00 2.70 98.52 0.00 96.33 0.00 62.04 0.35 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.367628524
93.10 0.43 98.89 0.00 95.27 0.00 97.63 0.00 100.00 0.00 98.52 0.00 96.33 0.00 65.06 3.02 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_clock_gating.3037737017
93.48 0.38 98.92 0.03 95.39 0.12 99.76 2.13 100.00 0.00 98.58 0.06 96.49 0.17 65.19 0.12 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.1182964459
93.85 0.37 98.92 0.00 95.64 0.25 99.76 0.00 100.00 0.00 98.64 0.06 96.66 0.17 67.33 2.15 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all.3441225615
94.16 0.31 98.92 0.00 95.72 0.08 99.76 0.00 100.00 0.00 98.64 0.00 96.83 0.17 69.25 1.92 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_both.1657508268
94.45 0.29 98.92 0.00 95.72 0.00 99.76 0.00 100.00 0.00 98.64 0.00 96.83 0.00 71.25 2.00 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_clock_gating.412700906
94.70 0.26 98.92 0.00 95.76 0.04 99.76 0.00 100.00 0.00 98.64 0.00 96.83 0.00 73.00 1.75 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2621228069
94.93 0.22 98.92 0.00 95.76 0.00 99.76 0.00 100.00 0.00 98.64 0.00 96.83 0.00 74.57 1.57 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.763460581
95.14 0.22 98.92 0.00 95.76 0.00 99.76 0.00 100.00 0.00 98.64 0.00 96.83 0.00 76.09 1.52 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_both.2622659172
95.36 0.22 98.98 0.06 95.92 0.16 99.76 0.00 100.00 0.00 98.76 0.12 98.00 1.17 76.09 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1292282255
95.55 0.19 98.98 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.76 0.00 98.00 0.00 77.44 1.35 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_both.1715775881
95.68 0.13 98.98 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.76 0.00 98.00 0.00 78.36 0.92 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all.1306023448
95.81 0.12 98.98 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.76 0.00 98.00 0.00 79.21 0.85 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.4290347957
95.92 0.12 98.98 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.76 0.00 98.00 0.00 80.03 0.82 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup.2095492440
96.03 0.11 98.98 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.76 0.00 98.00 0.00 80.81 0.77 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup.2488238418
96.12 0.09 98.98 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.76 0.00 98.00 0.00 81.41 0.60 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt.3786178902
96.20 0.08 98.98 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.76 0.00 98.00 0.00 81.96 0.55 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2544902924
96.27 0.07 98.98 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.76 0.00 98.00 0.00 82.48 0.52 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all.215052148
96.35 0.07 99.07 0.09 96.05 0.12 100.00 0.24 100.00 0.00 98.83 0.06 98.00 0.00 82.48 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_alert_test.142294055
96.42 0.07 99.07 0.00 96.05 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.00 0.00 82.98 0.50 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_stress_all.2643574195
96.48 0.06 99.07 0.00 96.05 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.00 0.00 83.43 0.45 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup.271967390
96.54 0.06 99.07 0.00 96.05 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.00 0.00 83.85 0.42 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_stress_all.581532851
96.60 0.06 99.07 0.00 96.29 0.25 100.00 0.00 100.00 0.00 98.83 0.00 98.00 0.00 84.03 0.17 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3955230908
96.66 0.06 99.07 0.00 96.29 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.16 0.17 84.28 0.25 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.1813107586
96.72 0.05 99.07 0.00 96.29 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.16 0.00 84.65 0.37 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all.347428737
96.77 0.05 99.07 0.00 96.29 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.16 0.00 85.03 0.37 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_both.1123285456
96.82 0.05 99.07 0.00 96.29 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.16 0.00 85.40 0.37 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_both.938521527
96.87 0.05 99.07 0.00 96.29 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.16 0.00 85.72 0.32 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all.3558577660
96.91 0.04 99.07 0.00 96.50 0.21 100.00 0.00 100.00 0.00 98.83 0.00 98.16 0.00 85.80 0.07 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3481775031
96.95 0.04 99.07 0.00 96.50 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.16 0.00 86.07 0.27 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_interrupt.872396366
96.98 0.04 99.07 0.00 96.50 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.16 0.00 86.32 0.25 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all.1559157613
97.02 0.04 99.07 0.00 96.50 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.16 0.00 86.57 0.25 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all.2618726643
97.06 0.04 99.07 0.00 96.58 0.08 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.17 86.57 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3914336110
97.09 0.03 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 86.80 0.22 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup.2855739045
97.12 0.03 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 87.00 0.20 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.3300841288
97.14 0.03 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 87.20 0.20 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt.3099696420
97.17 0.02 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 87.37 0.17 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_both.783254139
97.19 0.02 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 87.55 0.17 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_clock_gating.3107657000
97.22 0.02 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 87.72 0.17 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_wakeup.1263208417
97.24 0.02 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 87.87 0.15 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_clock_gating.4275797014
97.26 0.02 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 88.02 0.15 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_stress_all.752423832
97.28 0.02 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 88.17 0.15 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_polled.3043727697
97.30 0.02 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 88.32 0.15 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup.1793137091
97.33 0.02 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 88.47 0.15 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.2250462491
97.34 0.02 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 88.59 0.12 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_fsm_reset.2081594534
97.36 0.02 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 88.72 0.12 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_clock_gating.2925948077
97.38 0.01 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 88.82 0.10 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.2865873762
97.39 0.01 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 88.92 0.10 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled.2147625477
97.40 0.01 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.02 0.10 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_interrupt.3215072452
97.42 0.01 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.12 0.10 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_both.525307241
97.43 0.01 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.22 0.10 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_wakeup.1553956319
97.45 0.01 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.32 0.10 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_wakeup.2424144067
97.46 0.01 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.42 0.10 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_clock_gating.670496895
97.48 0.01 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.52 0.10 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_both.2394240226
97.49 0.01 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.62 0.10 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_both.3918373113
97.50 0.01 99.07 0.00 96.67 0.08 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.62 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.50953041
97.51 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.69 0.07 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all.437031705
97.52 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.77 0.07 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all.1000397180
97.53 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.84 0.07 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt.2797417028
97.54 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.92 0.07 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_interrupt.4038673885
97.56 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.99 0.07 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_stress_all.2292361776
97.57 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.07 0.07 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_interrupt.3360298533
97.58 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.14 0.07 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_both.1886190555
97.59 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.22 0.07 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_fsm_reset.3541961245
97.60 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.29 0.07 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all.4290474405
97.61 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.34 0.05 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3922303270
97.61 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.39 0.05 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3754737036
97.62 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.44 0.05 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt.3098894910
97.63 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.49 0.05 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_fsm_reset.841209983
97.63 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.54 0.05 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled.2533922091
97.64 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.59 0.05 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_clock_gating.1459683717
97.65 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.64 0.05 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_both.936767302
97.66 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.69 0.05 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all.1848645705
97.66 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.74 0.05 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_interrupt.1580657464
97.67 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.79 0.05 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1572674276
97.68 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.84 0.05 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_stress_all.607230736
97.68 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.87 0.02 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.1111094393
97.68 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.89 0.02 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_clock_gating.387117558
97.69 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.92 0.02 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_fsm_reset.1030987852
97.69 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.94 0.02 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_interrupt.1101152189
97.69 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.97 0.02 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_both.403591911
97.70 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.99 0.02 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_stress_all.2211269567
97.70 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 91.02 0.02 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_stress_all.2110140794

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2187841243
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.4201716624
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.4282857837
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3626957449
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.630183916
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.1465249007
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2502970583
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3397683363
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3856711563
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3617886978
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.908176330
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1002454989
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2327398453
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.4118531663
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1144089174
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1473016909
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3495335976
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.2833456717
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1379808865
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.598634244
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3479013027
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1090157316
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.3166563599
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.215963256
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.944565300
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2567890586
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.256139232
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1336976390
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.4120278274
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3043014251
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.931453295
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3820174874
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3735696400
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1043956321
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.105379389
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.212724207
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3651119981
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3129373525
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1676995659
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1045177076
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.4191849555
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.68103377
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.4243737368
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2741885796
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1156002916
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2414968039
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.3944252938
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.4183132868
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3568811527
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2114690498
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1985534852
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3662452914
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.1565666163
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3358009153
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1878169978
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1399996956
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2976234030
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2160085176
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.723516666
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.4274563164
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2280647601
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1598146002
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.4269308710
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2226320282
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.1941896900
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.556824267
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1479815708
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2012866557
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2689256906
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2794231797
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.281464066
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3758912531
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3378799817
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1289593804
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2866891629
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.4120799
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2419199018
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2149137294
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.3209758902
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.499470139
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1938344343
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.3229122670
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.3213182757
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.3666332151
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.3441149798
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.2535014801
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.2984635832
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.2496507766
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.805398176
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.3160594371
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.2110818150
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.845264537
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.983443003
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3543355741
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3066415206
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3102485258
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.89682822
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.4255885626
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.4156907156
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3324980390
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/30.adc_ctrl_intr_test.3542833224
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/31.adc_ctrl_intr_test.1287072948
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/32.adc_ctrl_intr_test.2413165897
/workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/cover_reg_top/33.adc_ctrl_intr_test.1392143040
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Total test records in report: 919
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.1595531667 Aug 25 02:22:47 AM UTC 24 Aug 25 02:22:50 AM UTC 24 295960677 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.1182964459 Aug 25 02:22:47 AM UTC 24 Aug 25 02:22:50 AM UTC 24 4214409417 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_poweron_counter.3983622837 Aug 25 02:22:46 AM UTC 24 Aug 25 02:22:52 AM UTC 24 5145216253 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_alert_test.142294055 Aug 25 02:22:54 AM UTC 24 Aug 25 02:22:58 AM UTC 24 481076561 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_poweron_counter.3420734827 Aug 25 02:22:52 AM UTC 24 Aug 25 02:23:04 AM UTC 24 3736358040 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_alert_test.4198069356 Aug 25 02:23:03 AM UTC 24 Aug 25 02:23:05 AM UTC 24 535590984 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_poweron_counter.1037313587 Aug 25 02:22:58 AM UTC 24 Aug 25 02:23:08 AM UTC 24 3110401253 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.3773635009 Aug 25 02:22:46 AM UTC 24 Aug 25 02:23:08 AM UTC 24 2062264175 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_clock_gating.1681629252 Aug 25 02:22:46 AM UTC 24 Aug 25 02:23:09 AM UTC 24 163614692078 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_sec_cm.3233356582 Aug 25 02:22:53 AM UTC 24 Aug 25 02:23:12 AM UTC 24 7973671498 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_smoke.886852666 Aug 25 02:22:43 AM UTC 24 Aug 25 02:23:13 AM UTC 24 6025651632 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_smoke.2486320899 Aug 25 02:23:05 AM UTC 24 Aug 25 02:23:14 AM UTC 24 6112884495 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3749596230 Aug 25 02:22:53 AM UTC 24 Aug 25 02:23:15 AM UTC 24 62393106829 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_smoke.554646587 Aug 25 02:22:47 AM UTC 24 Aug 25 02:23:19 AM UTC 24 5918475232 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1725305722 Aug 25 02:23:00 AM UTC 24 Aug 25 02:23:19 AM UTC 24 7670165185 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_poweron_counter.1207927231 Aug 25 02:23:16 AM UTC 24 Aug 25 02:23:22 AM UTC 24 4571015956 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_smoke.609250712 Aug 25 02:22:54 AM UTC 24 Aug 25 02:23:24 AM UTC 24 6073366892 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_alert_test.4040640405 Aug 25 02:23:25 AM UTC 24 Aug 25 02:23:27 AM UTC 24 322476250 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_smoke.445293481 Aug 25 02:23:25 AM UTC 24 Aug 25 02:23:30 AM UTC 24 6010588309 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_sec_cm.1169186828 Aug 25 02:23:23 AM UTC 24 Aug 25 02:23:43 AM UTC 24 8106974419 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_sec_cm.173908935 Aug 25 02:23:03 AM UTC 24 Aug 25 02:23:46 AM UTC 24 8495907682 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_poweron_counter.3467283475 Aug 25 02:23:45 AM UTC 24 Aug 25 02:23:58 AM UTC 24 4704472343 ps
T391 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_alert_test.1084094417 Aug 25 02:23:58 AM UTC 24 Aug 25 02:24:01 AM UTC 24 438757668 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2033989126 Aug 25 02:23:19 AM UTC 24 Aug 25 02:24:10 AM UTC 24 53198198552 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1489432048 Aug 25 02:23:49 AM UTC 24 Aug 25 02:24:15 AM UTC 24 5354150870 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_smoke.1396298728 Aug 25 02:23:58 AM UTC 24 Aug 25 02:24:15 AM UTC 24 5657109947 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_sec_cm.279041440 Aug 25 02:23:54 AM UTC 24 Aug 25 02:24:19 AM UTC 24 8222626109 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_lowpower_counter.3129483906 Aug 25 02:22:46 AM UTC 24 Aug 25 02:24:22 AM UTC 24 43836176765 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_alert_test.877889735 Aug 25 02:24:21 AM UTC 24 Aug 25 02:24:23 AM UTC 24 541670411 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.1813107586 Aug 25 02:22:57 AM UTC 24 Aug 25 02:24:30 AM UTC 24 377075456075 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_poweron_counter.234184519 Aug 25 02:24:16 AM UTC 24 Aug 25 02:24:39 AM UTC 24 4595794417 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3481775031 Aug 25 02:24:20 AM UTC 24 Aug 25 02:24:43 AM UTC 24 68825325655 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_lowpower_counter.1877676671 Aug 25 02:22:52 AM UTC 24 Aug 25 02:24:47 AM UTC 24 34902990116 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_smoke.331375992 Aug 25 02:24:23 AM UTC 24 Aug 25 02:24:49 AM UTC 24 5807788608 ps
T125 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_poweron_counter.2295128231 Aug 25 02:24:46 AM UTC 24 Aug 25 02:24:54 AM UTC 24 4616428768 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled_fixed.3256842731 Aug 25 02:22:47 AM UTC 24 Aug 25 02:24:55 AM UTC 24 168098110510 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_lowpower_counter.1131001115 Aug 25 02:22:59 AM UTC 24 Aug 25 02:24:58 AM UTC 24 26599087168 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_clock_gating.718649987 Aug 25 02:23:12 AM UTC 24 Aug 25 02:24:59 AM UTC 24 164386276803 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_alert_test.3404635022 Aug 25 02:24:57 AM UTC 24 Aug 25 02:24:59 AM UTC 24 281764116 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.690132141 Aug 25 02:24:50 AM UTC 24 Aug 25 02:25:03 AM UTC 24 15079154870 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.3300841288 Aug 25 02:22:52 AM UTC 24 Aug 25 02:25:24 AM UTC 24 349612702171 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_smoke.2750289249 Aug 25 02:24:59 AM UTC 24 Aug 25 02:25:25 AM UTC 24 5797507502 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2621228069 Aug 25 02:22:51 AM UTC 24 Aug 25 02:25:28 AM UTC 24 162902599633 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_poweron_counter.1559190073 Aug 25 02:25:28 AM UTC 24 Aug 25 02:25:32 AM UTC 24 3847749649 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_lowpower_counter.429638087 Aug 25 02:23:47 AM UTC 24 Aug 25 02:25:53 AM UTC 24 29956526649 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_lowpower_counter.1419353757 Aug 25 02:25:32 AM UTC 24 Aug 25 02:25:58 AM UTC 24 38248633471 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1178691458 Aug 25 02:24:00 AM UTC 24 Aug 25 02:26:01 AM UTC 24 166423705708 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_lowpower_counter.2989469089 Aug 25 02:23:16 AM UTC 24 Aug 25 02:26:06 AM UTC 24 44327128957 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_alert_test.2203377086 Aug 25 02:26:03 AM UTC 24 Aug 25 02:26:07 AM UTC 24 362739058 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled.709605256 Aug 25 02:23:05 AM UTC 24 Aug 25 02:26:17 AM UTC 24 498954663674 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt.1170566207 Aug 25 02:23:09 AM UTC 24 Aug 25 02:26:17 AM UTC 24 170089251603 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_smoke.3280773790 Aug 25 02:26:03 AM UTC 24 Aug 25 02:26:18 AM UTC 24 5935151905 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.2973054951 Aug 25 02:25:59 AM UTC 24 Aug 25 02:26:21 AM UTC 24 10161895666 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_lowpower_counter.1974440100 Aug 25 02:24:48 AM UTC 24 Aug 25 02:26:22 AM UTC 24 41131395501 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_poweron_counter.2758063234 Aug 25 02:26:22 AM UTC 24 Aug 25 02:26:26 AM UTC 24 2633901095 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_alert_test.363703123 Aug 25 02:26:28 AM UTC 24 Aug 25 02:26:31 AM UTC 24 521600515 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_both.1615255271 Aug 25 02:22:52 AM UTC 24 Aug 25 02:26:43 AM UTC 24 348783348486 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1516640108 Aug 25 02:26:27 AM UTC 24 Aug 25 02:26:53 AM UTC 24 2280953541 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_smoke.2033808344 Aug 25 02:26:31 AM UTC 24 Aug 25 02:27:00 AM UTC 24 6006373267 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_lowpower_counter.2649637032 Aug 25 02:24:16 AM UTC 24 Aug 25 02:27:01 AM UTC 24 40724660472 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled.3630310166 Aug 25 02:22:47 AM UTC 24 Aug 25 02:27:23 AM UTC 24 161524866993 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt_fixed.1284118394 Aug 25 02:23:09 AM UTC 24 Aug 25 02:27:31 AM UTC 24 164981873234 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all.3441225615 Aug 25 02:23:50 AM UTC 24 Aug 25 02:27:33 AM UTC 24 370649993838 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_poweron_counter.3843573186 Aug 25 02:27:32 AM UTC 24 Aug 25 02:27:37 AM UTC 24 3384338797 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all.1821246995 Aug 25 02:24:54 AM UTC 24 Aug 25 02:27:41 AM UTC 24 169863976986 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2281254506 Aug 25 02:26:09 AM UTC 24 Aug 25 02:27:42 AM UTC 24 162667940027 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled.1483724382 Aug 25 02:24:59 AM UTC 24 Aug 25 02:27:51 AM UTC 24 167526428693 ps
T392 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_alert_test.1686719445 Aug 25 02:27:52 AM UTC 24 Aug 25 02:27:55 AM UTC 24 415426791 ps
T393 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled_fixed.2412217310 Aug 25 02:23:06 AM UTC 24 Aug 25 02:27:56 AM UTC 24 169734092783 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1296225118 Aug 25 02:24:02 AM UTC 24 Aug 25 02:27:56 AM UTC 24 608391761945 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled_fixed.2333934792 Aug 25 02:24:29 AM UTC 24 Aug 25 02:27:56 AM UTC 24 164191719858 ps
T394 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_smoke.1088041860 Aug 25 02:27:56 AM UTC 24 Aug 25 02:28:04 AM UTC 24 5682077987 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled.2894722661 Aug 25 02:22:43 AM UTC 24 Aug 25 02:28:05 AM UTC 24 163854994078 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.1670074818 Aug 25 02:24:31 AM UTC 24 Aug 25 02:28:14 AM UTC 24 323645673173 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup_fixed.1461595370 Aug 25 02:23:39 AM UTC 24 Aug 25 02:28:16 AM UTC 24 620356988573 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_both.1657508268 Aug 25 02:22:46 AM UTC 24 Aug 25 02:28:27 AM UTC 24 337005616755 ps
T395 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_lowpower_counter.2867666259 Aug 25 02:26:23 AM UTC 24 Aug 25 02:28:30 AM UTC 24 29187721541 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup.1175912593 Aug 25 02:27:03 AM UTC 24 Aug 25 02:28:48 AM UTC 24 162628128790 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2544902924 Aug 25 02:22:56 AM UTC 24 Aug 25 02:28:55 AM UTC 24 185921323942 ps
T396 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_poweron_counter.1089022954 Aug 25 02:28:31 AM UTC 24 Aug 25 02:28:57 AM UTC 24 5487589443 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.4036106061 Aug 25 02:27:42 AM UTC 24 Aug 25 02:28:59 AM UTC 24 34223987839 ps
T397 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_alert_test.1379220981 Aug 25 02:29:03 AM UTC 24 Aug 25 02:29:06 AM UTC 24 462498615 ps
T398 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled_fixed.1470390545 Aug 25 02:24:00 AM UTC 24 Aug 25 02:29:23 AM UTC 24 168316888426 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.4290347957 Aug 25 02:28:58 AM UTC 24 Aug 25 02:29:30 AM UTC 24 54576834720 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt.3786178902 Aug 25 02:25:00 AM UTC 24 Aug 25 02:29:30 AM UTC 24 329142500248 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup.2488238418 Aug 25 02:23:10 AM UTC 24 Aug 25 02:29:30 AM UTC 24 345946328893 ps
T399 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_lowpower_counter.823686524 Aug 25 02:28:49 AM UTC 24 Aug 25 02:29:32 AM UTC 24 41991518707 ps
T400 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_smoke.883527757 Aug 25 02:29:06 AM UTC 24 Aug 25 02:29:33 AM UTC 24 5943565438 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup.1767455742 Aug 25 02:24:40 AM UTC 24 Aug 25 02:29:33 AM UTC 24 352450556492 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all.2618726643 Aug 25 02:26:01 AM UTC 24 Aug 25 02:30:20 AM UTC 24 382691664046 ps
T401 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_lowpower_counter.2018109123 Aug 25 02:27:34 AM UTC 24 Aug 25 02:30:35 AM UTC 24 48552833606 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_clock_gating.759495862 Aug 25 02:24:12 AM UTC 24 Aug 25 02:30:47 AM UTC 24 493370182878 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_poweron_counter.1732364150 Aug 25 02:30:36 AM UTC 24 Aug 25 02:30:52 AM UTC 24 3074403499 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup_fixed.51925139 Aug 25 02:25:04 AM UTC 24 Aug 25 02:31:15 AM UTC 24 403821701175 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.1111094393 Aug 25 02:31:16 AM UTC 24 Aug 25 02:31:26 AM UTC 24 18485459862 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup.1918975396 Aug 25 02:23:35 AM UTC 24 Aug 25 02:31:31 AM UTC 24 378402466865 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_alert_test.2588650796 Aug 25 02:31:32 AM UTC 24 Aug 25 02:31:35 AM UTC 24 436053472 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.1885464939 Aug 25 02:28:05 AM UTC 24 Aug 25 02:31:36 AM UTC 24 186993864490 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt.3535102483 Aug 25 02:29:30 AM UTC 24 Aug 25 02:31:40 AM UTC 24 158608360895 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_fsm_reset.3489779829 Aug 25 02:22:59 AM UTC 24 Aug 25 02:31:46 AM UTC 24 75635699481 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all.2749724272 Aug 25 02:31:27 AM UTC 24 Aug 25 02:31:47 AM UTC 24 182755250745 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled.3660129236 Aug 25 02:26:34 AM UTC 24 Aug 25 02:31:54 AM UTC 24 161860239982 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_smoke.2912926968 Aug 25 02:31:35 AM UTC 24 Aug 25 02:31:56 AM UTC 24 5722403905 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt.464282731 Aug 25 02:26:07 AM UTC 24 Aug 25 02:32:04 AM UTC 24 323519781455 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled.1991765112 Aug 25 02:29:23 AM UTC 24 Aug 25 02:32:07 AM UTC 24 169905780474 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_clock_gating.247944245 Aug 25 02:24:44 AM UTC 24 Aug 25 02:32:09 AM UTC 24 501304590784 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_poweron_counter.1804748845 Aug 25 02:32:08 AM UTC 24 Aug 25 02:32:14 AM UTC 24 3401196428 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled_fixed.3918161267 Aug 25 02:26:45 AM UTC 24 Aug 25 02:32:22 AM UTC 24 327481025383 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.2168547271 Aug 25 02:32:22 AM UTC 24 Aug 25 02:32:32 AM UTC 24 3360101577 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled_fixed.2025824453 Aug 25 02:22:55 AM UTC 24 Aug 25 02:32:40 AM UTC 24 161389655974 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1327754268 Aug 25 02:26:18 AM UTC 24 Aug 25 02:32:41 AM UTC 24 199131497913 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_alert_test.1858216763 Aug 25 02:32:41 AM UTC 24 Aug 25 02:32:43 AM UTC 24 382874615 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt.3704418228 Aug 25 02:26:45 AM UTC 24 Aug 25 02:32:44 AM UTC 24 162923615858 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt.3573458307 Aug 25 02:24:00 AM UTC 24 Aug 25 02:32:49 AM UTC 24 494245255193 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_lowpower_counter.1779443990 Aug 25 02:30:47 AM UTC 24 Aug 25 02:32:54 AM UTC 24 39522032446 ps
T402 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_smoke.3838175902 Aug 25 02:32:42 AM UTC 24 Aug 25 02:33:08 AM UTC 24 5769033944 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_both.3089078458 Aug 25 02:27:24 AM UTC 24 Aug 25 02:33:12 AM UTC 24 338623943840 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled_fixed.3782589364 Aug 25 02:22:44 AM UTC 24 Aug 25 02:33:43 AM UTC 24 330988577664 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt.3998035280 Aug 25 02:22:44 AM UTC 24 Aug 25 02:33:44 AM UTC 24 162267512113 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled.2569431513 Aug 25 02:24:25 AM UTC 24 Aug 25 02:34:02 AM UTC 24 326392820092 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_poweron_counter.4053836983 Aug 25 02:34:02 AM UTC 24 Aug 25 02:34:11 AM UTC 24 3398650571 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.2155765571 Aug 25 02:22:57 AM UTC 24 Aug 25 02:34:18 AM UTC 24 328562953820 ps
T405 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled_fixed.3097077921 Aug 25 02:23:29 AM UTC 24 Aug 25 02:34:23 AM UTC 24 161486923915 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt.3415834042 Aug 25 02:23:29 AM UTC 24 Aug 25 02:34:23 AM UTC 24 163986082073 ps
T406 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1550477763 Aug 25 02:29:31 AM UTC 24 Aug 25 02:34:31 AM UTC 24 503697473497 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all.2224187129 Aug 25 02:22:46 AM UTC 24 Aug 25 02:34:34 AM UTC 24 203219499321 ps
T407 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_alert_test.2810312093 Aug 25 02:34:32 AM UTC 24 Aug 25 02:34:35 AM UTC 24 281506192 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_fsm_reset.3541961245 Aug 25 02:24:18 AM UTC 24 Aug 25 02:34:36 AM UTC 24 91367292873 ps
T408 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled_fixed.216677868 Aug 25 02:32:45 AM UTC 24 Aug 25 02:34:37 AM UTC 24 166292485106 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt_fixed.3730576084 Aug 25 02:31:48 AM UTC 24 Aug 25 02:34:41 AM UTC 24 166415043283 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_clock_gating.1315986532 Aug 25 02:23:43 AM UTC 24 Aug 25 02:34:42 AM UTC 24 165124497062 ps
T410 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_smoke.4153824995 Aug 25 02:34:35 AM UTC 24 Aug 25 02:34:43 AM UTC 24 5659118877 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3754737036 Aug 25 02:34:24 AM UTC 24 Aug 25 02:34:45 AM UTC 24 10461263531 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup_fixed.94263663 Aug 25 02:23:11 AM UTC 24 Aug 25 02:34:48 AM UTC 24 605176956754 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all.3649536150 Aug 25 02:23:01 AM UTC 24 Aug 25 02:34:49 AM UTC 24 153885258494 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_poweron_counter.2486751252 Aug 25 02:34:49 AM UTC 24 Aug 25 02:34:55 AM UTC 24 3376875104 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_both.3409690607 Aug 25 02:24:46 AM UTC 24 Aug 25 02:34:58 AM UTC 24 161366040240 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_lowpower_counter.1863855623 Aug 25 02:32:09 AM UTC 24 Aug 25 02:35:08 AM UTC 24 40859525854 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_clock_gating.11318523 Aug 25 02:29:34 AM UTC 24 Aug 25 02:35:10 AM UTC 24 377218485914 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.2802593375 Aug 25 02:23:16 AM UTC 24 Aug 25 02:35:13 AM UTC 24 127743250672 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all.3558577660 Aug 25 02:24:20 AM UTC 24 Aug 25 02:35:16 AM UTC 24 508041497404 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_alert_test.3173802642 Aug 25 02:35:14 AM UTC 24 Aug 25 02:35:17 AM UTC 24 464059823 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_lowpower_counter.3990727090 Aug 25 02:34:55 AM UTC 24 Aug 25 02:35:19 AM UTC 24 33208311204 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_fsm_reset.1287921462 Aug 25 02:26:26 AM UTC 24 Aug 25 02:35:20 AM UTC 24 86856841756 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled.2533922091 Aug 25 02:22:54 AM UTC 24 Aug 25 02:35:25 AM UTC 24 491298838311 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt_fixed.862888360 Aug 25 02:26:55 AM UTC 24 Aug 25 02:35:31 AM UTC 24 493129874030 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled_fixed.1719940985 Aug 25 02:24:59 AM UTC 24 Aug 25 02:35:31 AM UTC 24 163720679565 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.1565079171 Aug 25 02:35:09 AM UTC 24 Aug 25 02:35:34 AM UTC 24 24023640889 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_lowpower_counter.2219036762 Aug 25 02:34:12 AM UTC 24 Aug 25 02:35:36 AM UTC 24 41089307624 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled.2247714982 Aug 25 02:23:58 AM UTC 24 Aug 25 02:35:37 AM UTC 24 328816727595 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_poweron_counter.198408344 Aug 25 02:35:36 AM UTC 24 Aug 25 02:35:42 AM UTC 24 2986268678 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_smoke.3721443334 Aug 25 02:35:17 AM UTC 24 Aug 25 02:35:43 AM UTC 24 6049729828 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt_fixed.551266550 Aug 25 02:24:33 AM UTC 24 Aug 25 02:35:46 AM UTC 24 165326500403 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_both.1089378799 Aug 25 02:25:26 AM UTC 24 Aug 25 02:35:48 AM UTC 24 512173011867 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_both.2212624454 Aug 25 02:32:05 AM UTC 24 Aug 25 02:35:52 AM UTC 24 180570748544 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_alert_test.1004670984 Aug 25 02:35:49 AM UTC 24 Aug 25 02:35:52 AM UTC 24 400445826 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.3691543157 Aug 25 02:35:45 AM UTC 24 Aug 25 02:35:56 AM UTC 24 36838473547 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_smoke.3069590570 Aug 25 02:35:53 AM UTC 24 Aug 25 02:36:01 AM UTC 24 5748496007 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup.3497947762 Aug 25 02:29:34 AM UTC 24 Aug 25 02:36:05 AM UTC 24 201923214504 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt_fixed.761142371 Aug 25 02:32:55 AM UTC 24 Aug 25 02:36:08 AM UTC 24 167598875212 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all.2067987059 Aug 25 02:26:27 AM UTC 24 Aug 25 02:36:22 AM UTC 24 325003895693 ps
T387 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_fsm_reset.4000520438 Aug 25 02:25:54 AM UTC 24 Aug 25 02:36:44 AM UTC 24 96383133593 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1709348380 Aug 25 02:35:26 AM UTC 24 Aug 25 02:36:50 AM UTC 24 169691377036 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup.2095492440 Aug 25 02:24:02 AM UTC 24 Aug 25 02:36:52 AM UTC 24 364856244750 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2811076564 Aug 25 02:22:44 AM UTC 24 Aug 25 02:36:58 AM UTC 24 197495952248 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_poweron_counter.2964887002 Aug 25 02:36:53 AM UTC 24 Aug 25 02:36:59 AM UTC 24 4664139491 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_fsm_reset.136184907 Aug 25 02:22:46 AM UTC 24 Aug 25 02:37:05 AM UTC 24 100787382050 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.251694126 Aug 25 02:37:06 AM UTC 24 Aug 25 02:37:15 AM UTC 24 9289381980 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup_fixed.305510925 Aug 25 02:22:51 AM UTC 24 Aug 25 02:37:15 AM UTC 24 215883885302 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_alert_test.3110626630 Aug 25 02:37:16 AM UTC 24 Aug 25 02:37:19 AM UTC 24 370927592 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_clock_gating.2862476618 Aug 25 02:34:45 AM UTC 24 Aug 25 02:37:23 AM UTC 24 342951143699 ps
T425 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt_fixed.3661232466 Aug 25 02:34:42 AM UTC 24 Aug 25 02:37:33 AM UTC 24 162446149886 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_smoke.2392872185 Aug 25 02:37:20 AM UTC 24 Aug 25 02:37:37 AM UTC 24 5805387079 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all.3691280259 Aug 25 02:23:22 AM UTC 24 Aug 25 02:37:37 AM UTC 24 400907493162 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2510333307 Aug 25 02:27:03 AM UTC 24 Aug 25 02:37:45 AM UTC 24 384710261387 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_lowpower_counter.3744960044 Aug 25 02:36:59 AM UTC 24 Aug 25 02:37:48 AM UTC 24 46321016339 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.1437561549 Aug 25 02:22:53 AM UTC 24 Aug 25 02:37:56 AM UTC 24 238730135121 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all.4290474405 Aug 25 02:27:43 AM UTC 24 Aug 25 02:37:58 AM UTC 24 397337742914 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup_fixed.2386320780 Aug 25 02:24:40 AM UTC 24 Aug 25 02:37:58 AM UTC 24 204738461920 ps
T430 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_poweron_counter.566985234 Aug 25 02:37:59 AM UTC 24 Aug 25 02:38:02 AM UTC 24 3945390923 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_lowpower_counter.4164548571 Aug 25 02:35:37 AM UTC 24 Aug 25 02:38:06 AM UTC 24 34048773139 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_fsm_reset.7218755 Aug 25 02:22:53 AM UTC 24 Aug 25 02:38:17 AM UTC 24 119592854797 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_fsm_reset.421259479 Aug 25 02:24:50 AM UTC 24 Aug 25 02:38:19 AM UTC 24 99746634444 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt.3617947191 Aug 25 02:32:50 AM UTC 24 Aug 25 02:38:33 AM UTC 24 332420337740 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_lowpower_counter.70603334 Aug 25 02:38:03 AM UTC 24 Aug 25 02:38:35 AM UTC 24 28984969776 ps
T433 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_alert_test.1070253026 Aug 25 02:38:34 AM UTC 24 Aug 25 02:38:36 AM UTC 24 496454558 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_clock_gating.3326605744 Aug 25 02:27:04 AM UTC 24 Aug 25 02:38:43 AM UTC 24 164449571954 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1770532641 Aug 25 02:38:18 AM UTC 24 Aug 25 02:38:45 AM UTC 24 10214522198 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_clock_gating.3785655881 Aug 25 02:35:35 AM UTC 24 Aug 25 02:38:50 AM UTC 24 178140169799 ps
T434 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt_fixed.343902355 Aug 25 02:22:56 AM UTC 24 Aug 25 02:38:53 AM UTC 24 495645478529 ps
T435 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup_fixed.668332499 Aug 25 02:31:57 AM UTC 24 Aug 25 02:38:56 AM UTC 24 403085611419 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_smoke.3793350036 Aug 25 02:38:36 AM UTC 24 Aug 25 02:39:02 AM UTC 24 6000202904 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt.3099696420 Aug 25 02:27:57 AM UTC 24 Aug 25 02:39:12 AM UTC 24 168159596602 ps
T339 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled.386341298 Aug 25 02:27:56 AM UTC 24 Aug 25 02:39:20 AM UTC 24 162898312138 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled.1977864415 Aug 25 02:34:36 AM UTC 24 Aug 25 02:39:21 AM UTC 24 326740966444 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_both.399313051 Aug 25 02:26:19 AM UTC 24 Aug 25 02:39:22 AM UTC 24 353358072522 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled.457670645 Aug 25 02:26:05 AM UTC 24 Aug 25 02:39:28 AM UTC 24 331183924508 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt_fixed.192331119 Aug 25 02:36:06 AM UTC 24 Aug 25 02:39:30 AM UTC 24 491216651169 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_clock_gating.1897752260 Aug 25 02:25:25 AM UTC 24 Aug 25 02:39:36 AM UTC 24 351434659154 ps
T438 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_poweron_counter.2986518198 Aug 25 02:39:22 AM UTC 24 Aug 25 02:39:37 AM UTC 24 3352891363 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.2250462491 Aug 25 02:27:38 AM UTC 24 Aug 25 02:39:40 AM UTC 24 99817568854 ps
T439 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_alert_test.982866667 Aug 25 02:39:37 AM UTC 24 Aug 25 02:39:40 AM UTC 24 411354490 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3393255152 Aug 25 02:39:29 AM UTC 24 Aug 25 02:39:40 AM UTC 24 11250792247 ps
T440 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt_fixed.993301476 Aug 25 02:22:44 AM UTC 24 Aug 25 02:39:43 AM UTC 24 499087892240 ps
T441 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_smoke.3156284137 Aug 25 02:39:38 AM UTC 24 Aug 25 02:39:52 AM UTC 24 5709040358 ps
T442 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2241338191 Aug 25 02:37:38 AM UTC 24 Aug 25 02:40:06 AM UTC 24 329447468228 ps
T443 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_lowpower_counter.1791996063 Aug 25 02:39:22 AM UTC 24 Aug 25 02:40:08 AM UTC 24 36286485641 ps
T444 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup_fixed.3046467892 Aug 25 02:33:12 AM UTC 24 Aug 25 02:40:10 AM UTC 24 404965816991 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_fsm_reset.1692822363 Aug 25 02:23:47 AM UTC 24 Aug 25 02:40:27 AM UTC 24 103214300867 ps
T445 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_poweron_counter.3116491979 Aug 25 02:40:28 AM UTC 24 Aug 25 02:40:42 AM UTC 24 2814538550 ps
T446 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled_fixed.1955163276 Aug 25 02:29:30 AM UTC 24 Aug 25 02:40:55 AM UTC 24 167196491172 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_both.2248433146 Aug 25 02:35:36 AM UTC 24 Aug 25 02:40:58 AM UTC 24 333386407366 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled_fixed.929187961 Aug 25 02:35:20 AM UTC 24 Aug 25 02:41:00 AM UTC 24 327183698604 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all.2608358655 Aug 25 02:35:47 AM UTC 24 Aug 25 02:41:00 AM UTC 24 350700284710 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_alert_test.2224013871 Aug 25 02:41:00 AM UTC 24 Aug 25 02:41:02 AM UTC 24 436899914 ps
T449 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_lowpower_counter.1834942078 Aug 25 02:40:43 AM UTC 24 Aug 25 02:41:07 AM UTC 24 23016702848 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.2259320311 Aug 25 02:40:59 AM UTC 24 Aug 25 02:41:11 AM UTC 24 25341608318 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_clock_gating.387117558 Aug 25 02:33:43 AM UTC 24 Aug 25 02:41:16 AM UTC 24 579811019204 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled.528382346 Aug 25 02:31:37 AM UTC 24 Aug 25 02:41:27 AM UTC 24 494304683920 ps
T450 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_smoke.710491405 Aug 25 02:41:03 AM UTC 24 Aug 25 02:41:29 AM UTC 24 5814253411 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_clock_gating.3037737017 Aug 25 02:36:44 AM UTC 24 Aug 25 02:41:35 AM UTC 24 533378816548 ps
T451 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup_fixed.770071653 Aug 25 02:28:15 AM UTC 24 Aug 25 02:41:40 AM UTC 24 207922782934 ps
T452 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled_fixed.2383558809 Aug 25 02:37:34 AM UTC 24 Aug 25 02:41:49 AM UTC 24 495922482067 ps
T453 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3497996074 Aug 25 02:40:07 AM UTC 24 Aug 25 02:41:52 AM UTC 24 200228987339 ps
T454 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_poweron_counter.611857228 Aug 25 02:41:53 AM UTC 24 Aug 25 02:41:59 AM UTC 24 4543537620 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled.3286759748 Aug 25 02:39:40 AM UTC 24 Aug 25 02:42:18 AM UTC 24 161260667035 ps
T455 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled_fixed.252599992 Aug 25 02:26:06 AM UTC 24 Aug 25 02:42:26 AM UTC 24 492022209649 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt.3682860894 Aug 25 02:37:37 AM UTC 24 Aug 25 02:42:50 AM UTC 24 335233790869 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup.2241880044 Aug 25 02:31:55 AM UTC 24 Aug 25 02:42:50 AM UTC 24 575038741655 ps
T365 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2170185017 Aug 25 02:42:27 AM UTC 24 Aug 25 02:42:53 AM UTC 24 9290284274 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_fsm_reset.2595462936 Aug 25 02:30:53 AM UTC 24 Aug 25 02:42:53 AM UTC 24 71978541702 ps
T456 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_alert_test.2773000310 Aug 25 02:42:51 AM UTC 24 Aug 25 02:42:55 AM UTC 24 507596628 ps
T457 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled_fixed.950591718 Aug 25 02:31:42 AM UTC 24 Aug 25 02:43:01 AM UTC 24 159025728575 ps
T347 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled.1391058237 Aug 25 02:32:44 AM UTC 24 Aug 25 02:43:04 AM UTC 24 164538178072 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup.3717220734 Aug 25 02:39:53 AM UTC 24 Aug 25 02:43:08 AM UTC 24 178408059873 ps
T458 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_smoke.3992596891 Aug 25 02:42:53 AM UTC 24 Aug 25 02:43:20 AM UTC 24 5769872385 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.2027389351 Aug 25 02:23:14 AM UTC 24 Aug 25 02:43:28 AM UTC 24 365302140185 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.763460581 Aug 25 02:28:17 AM UTC 24 Aug 25 02:43:45 AM UTC 24 545324561330 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt.2966700800 Aug 25 02:31:47 AM UTC 24 Aug 25 02:43:50 AM UTC 24 164651965390 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_both.3614504821 Aug 25 02:34:48 AM UTC 24 Aug 25 02:43:57 AM UTC 24 187916957772 ps
T342 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.2865873762 Aug 25 02:31:59 AM UTC 24 Aug 25 02:43:57 AM UTC 24 341621484042 ps
T459 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_poweron_counter.649394161 Aug 25 02:43:51 AM UTC 24 Aug 25 02:43:57 AM UTC 24 4476344810 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_fsm_reset.392605253 Aug 25 02:34:59 AM UTC 24 Aug 25 02:43:57 AM UTC 24 76206207146 ps
T460 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt_fixed.777162808 Aug 25 02:28:04 AM UTC 24 Aug 25 02:44:09 AM UTC 24 486616807908 ps
T461 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_alert_test.2786312855 Aug 25 02:44:10 AM UTC 24 Aug 25 02:44:12 AM UTC 24 409509521 ps
T462 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_lowpower_counter.4209952539 Aug 25 02:42:00 AM UTC 24 Aug 25 02:44:21 AM UTC 24 35502005896 ps
T463 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1450290864 Aug 25 02:38:50 AM UTC 24 Aug 25 02:44:25 AM UTC 24 167363102928 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled.1487182888 Aug 25 02:35:53 AM UTC 24 Aug 25 02:44:28 AM UTC 24 485187772877 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_fsm_reset.4111090646 Aug 25 02:28:56 AM UTC 24 Aug 25 02:44:42 AM UTC 24 115810655119 ps
T464 /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_smoke.133439166 Aug 25 02:44:13 AM UTC 24 Aug 25 02:44:42 AM UTC 24 6000536384 ps
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