Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22171

1

T3

19

T4

13

T5

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

18986

1

T3

19

T4

13

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

3185

1

T7

2

T10

5

T14

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16558

1

T3

19

T4

13

T5

11

auto[1]

5613

1

T10

3

T12

3

T13

6

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18427

1

T3

19

T4

13

T5

11

auto[1]

3744

1

T6

2

T7

1

T10

5

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	27	1			T234	18		T30	8		T235	1
values[1]	523	1			T7	2		T10	2		T68	2
values[2]	858	1			T13	6		T15	2		T59	37
values[3]	590	1			T12	3		T178	15		T34	15
values[4]	562	1			T236	1		T197	12		T237	1
values[5]	2682	1			T10	7		T14	5		T15	12
values[6]	623	1			T110	1		T177	11		T170	3
values[7]	631	1			T16	4		T62	3		T104	10
values[8]	712	1			T72	14		T73	6		T151	5
values[9]	1169	1			T18	19		T58	3		T186	1
minimum	13794	1			T3	19		T4	13		T5	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	810	1			T7	2		T10	2		T15	2
values[1]	746	1			T12	3		T13	6		T59	37
values[2]	494	1			T197	12		T238	12		T51	12
values[3]	2777	1			T15	12		T17	1		T60	9
values[4]	559	1			T10	7		T14	5		T110	1
values[5]	515	1			T62	1		T104	10		T177	11
values[6]	810	1			T16	4		T62	2		T72	25
values[7]	657	1			T72	14		T186	1		T239	1
values[8]	818	1			T18	19		T58	3		T187	6
values[9]	177	1			T240	10		T241	14		T50	22
minimum	13808	1			T3	19		T4	13		T5	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18399

1

T3

19

T4

13

T5

11

auto[1]

3772

1

T10

1

T13

2

T15

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T187	1		T143	13		T197	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T7	1		T10	1		T15	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T12	2		T13	5		T59	25
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T177	11		T34	15		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T197	3		T238	6		T51	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T242	1		T26	2		T243	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1485	1			T15	8		T17	1		T60	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T236	1		T244	8		T245	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T10	4		T140	3		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T10	2		T14	5		T110	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T104	1		T154	10		T246	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T62	1		T177	1		T170	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T16	4		T62	2		T24	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T72	14		T151	2		T140	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T72	9		T239	1		T170	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T186	1		T191	10		T197	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T18	9		T58	3		T187	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T37	1		T39	1		T247	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T240	1		T241	1		T248	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T50	11		T90	2		T249	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13692	1			T3	19		T4	13		T5	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T187	2		T143	9		T197	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T7	1		T10	1		T15	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T12	1		T13	1		T59	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T177	14		T250	1		T218	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T197	9		T238	6		T51	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T251	2		T196	10		T234	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	967	1			T15	4		T60	8		T61	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T244	19		T245	11		T180	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T140	7		T145	9		T252	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T10	1		T70	3		T141	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T104	9		T154	8		T253	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T177	10		T42	2		T53	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T156	9		T254	7		T255	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T72	11		T151	16		T140	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T72	5		T154	11		T145	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T197	9		T256	2		T182	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T18	10		T187	5		T73	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T37	5		T39	1		T257	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T240	9		T241	13		T248	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T50	11		T90	1		T258	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T6	2		T10	3		T12	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T234	9		T30	6		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T235	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T143	13		T197	13		T164	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T7	1		T10	1		T68	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T13	5		T59	25		T187	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T15	1		T177	11		T191	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T12	2		T178	15		T42	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T34	15		T244	8		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T197	3		T237	1		T145	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T236	1		T242	1		T26	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1447	1			T10	4		T15	8		T17	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T10	2		T14	5		T70	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T140	3		T154	10		T259	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T110	1		T177	1		T170	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T16	4		T62	2		T104	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T62	1		T72	14		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T72	9		T73	5		T170	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T151	1		T191	10		T197	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T18	9		T58	3		T239	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	351	1			T186	1		T37	1		T39	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13690	1			T3	19		T4	13		T5	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T234	9		T30	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T143	9		T197	9		T144	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T7	1		T10	1		T143	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T13	1		T59	12		T187	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T15	1		T177	14		T250	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T12	1		T42	11		T238	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T244	19		T218	1		T260	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T197	9		T145	9		T146	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T180	12		T261	2		T159	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	921	1			T15	4		T60	8		T61	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T10	1		T70	3		T141	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T140	7		T154	8		T252	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T177	10		T53	1		T262	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T104	9		T156	9		T263	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T72	11		T151	12		T140	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T72	5		T73	1		T145	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T151	4		T197	9		T256	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T18	10		T187	5		T154	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T37	5		T39	1		T50	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T6	2		T10	3		T12	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T187	3		T143	10		T197	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T7	2		T10	2		T15	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T12	3		T13	4		T59	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T177	15		T34	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T197	10		T238	7		T51	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T242	1		T26	1		T243	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T15	5		T17	1		T60	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T236	1		T244	20		T245	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T10	4		T140	8		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T10	2		T14	5		T110	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T104	10		T154	9		T246	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T62	1		T177	11		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T16	3		T62	2		T24	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T72	12		T151	18		T140	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T72	6		T239	1		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T186	1		T191	1		T197	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T18	11		T58	2		T187	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T37	6		T39	2		T247	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T240	10		T241	14		T248	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T50	12		T90	3		T249	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13808	1			T3	19		T4	13		T5	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T143	12		T197	12		T50	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T143	11		T191	13		T154	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	2		T59	23		T178	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T177	10		T34	14		T218	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T197	2		T238	5		T148	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T26	1		T192	9		T264	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1175	1			T15	7		T142	43		T188	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T244	7		T159	10		T161	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T140	2		T145	7		T259	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T10	1		T70	3		T141	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T154	9		T249	1		T265	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T170	2		T53	1		T266	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T16	1		T24	1		T34	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T72	13		T140	17		T267	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T72	8		T170	9		T36	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T191	9		T197	9		T256	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T18	8		T58	1		T73	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T157	11		T257	3		T160	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T248	5		T268	2		T269	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T50	10		T249	8		T258	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T234	10		T30	6		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T235	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T143	10		T197	10		T164	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T7	2		T10	2		T68	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	4		T59	14		T187	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T15	2		T177	15		T191	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	3		T178	1		T42	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T34	1		T244	20		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T197	10		T237	1		T145	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T236	1		T242	1		T26	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1233	1			T10	4		T15	5		T17	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T10	2		T14	5		T70	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T140	8		T154	9		T259	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T110	1		T177	11		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T16	3		T62	2		T104	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T62	1		T72	12		T151	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T72	6		T73	5		T170	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T151	5		T191	1		T197	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	344	1			T18	11		T58	2		T239	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T186	1		T37	6		T39	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13794	1			T3	19		T4	13		T5	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T234	8		T30	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T143	12		T197	12		T164	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T143	11		T154	10		T270	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T13	2		T59	23		T50	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T177	10		T191	13		T254	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T178	14		T238	5		T148	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T34	14		T244	7		T218	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T197	2		T145	7		T271	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T26	1		T159	10		T272	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1135	1			T15	7		T142	43		T188	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T10	1		T70	3		T141	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T140	2		T154	9		T259	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T170	2		T53	1		T148	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T16	1		T24	1		T34	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T72	13		T140	17		T267	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T72	8		T73	1		T170	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T191	9		T197	9		T256	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T18	8		T58	1		T154	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T50	10		T157	11		T249	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18399

1

T3

19

T4

13

T5

11

auto[1]

auto[0]

3772

1

T10

1

T13

2

T15

7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22171

1

T3

19

T4

13

T5

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

18866

1

T3

19

T4

13

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

3305

1

T7

2

T10

7

T14

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16759

1

T3

19

T4

13

T5

11

auto[1]

5412

1

T10

2

T12

3

T15

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18427

1

T3

19

T4

13

T5

11

auto[1]

3744

1

T6

2

T7

1

T10

5

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T273	1		-	-		-	-
values[0]	9	1			T274	1		T275	1		T276	7
values[1]	638	1			T62	1		T72	14		T177	25
values[2]	518	1			T10	4		T59	23		T177	11
values[3]	724	1			T187	3		T197	41		T36	9
values[4]	2601	1			T10	2		T17	1		T60	9
values[5]	544	1			T110	1		T170	10		T140	10
values[6]	807	1			T72	25		T151	5		T170	3
values[7]	720	1			T10	3		T12	3		T62	1
values[8]	629	1			T14	5		T104	10		T147	1
values[9]	1186	1			T7	2		T13	6		T15	14
minimum	13794	1			T3	19		T4	13		T5	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	780	1			T59	23		T62	1		T72	14
values[1]	595	1			T10	4		T177	11		T197	22
values[2]	649	1			T187	3		T197	19		T36	9
values[3]	2589	1			T17	1		T60	9		T61	7
values[4]	737	1			T10	2		T72	25		T151	5
values[5]	763	1			T12	3		T62	1		T151	13
values[6]	596	1			T10	3		T104	10		T143	22
values[7]	647	1			T7	2		T13	6		T14	5
values[8]	846	1			T15	12		T16	4		T58	3
values[9]	175	1			T18	19		T187	6		T197	12
minimum	13794	1			T3	19		T4	13		T5	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18399

1

T3

19

T4

13

T5

11

auto[1]

3772

1

T10

1

T13

2

T15

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T62	1		T177	11		T34	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T59	13		T72	9		T140	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T197	13		T141	9		T51	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T10	4		T177	1		T37	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T187	1		T36	9		T164	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T197	10		T147	1		T277	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1469	1			T17	1		T60	1		T61	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T186	1		T239	1		T70	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T10	1		T151	1		T170	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T72	14		T40	1		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T12	2		T62	1		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T191	10		T240	1		T241	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T104	1		T148	6		T278	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T10	2		T143	13		T39	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T13	5		T59	12		T178	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T7	1		T14	5		T15	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T16	4		T68	2		T236	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T15	8		T58	3		T62	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T197	3		T279	1		T280	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T18	9		T187	1		T237	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13690	1			T3	19		T4	13		T5	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T177	14		T42	11		T154	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T59	10		T72	5		T140	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T197	9		T141	8		T51	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T177	10		T37	5		T281	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T187	2		T267	6		T145	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T197	9		T277	12		T183	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	860	1			T60	8		T61	6		T111	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T70	3		T168	15		T282	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T10	1		T151	4		T140	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T72	11		T144	12		T50	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T12	1		T151	12		T283	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T240	9		T241	13		T90	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T104	9		T252	3		T284	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T10	1		T143	9		T39	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T13	1		T59	2		T146	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	1		T15	1		T144	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T73	1		T42	2		T50	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T15	4		T143	11		T154	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T197	9		T285	13		T286	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T18	10		T187	5		T287	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T6	2		T10	3		T12	2