Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22171

1

T3

19

T4

13

T5

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19018

1

T3

19

T4

13

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

3153

1

T10

6

T12

3

T13

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16204

1

T3

19

T4

13

T5

11

auto[1]

5967

1

T6

3

T10

3

T12

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18427

1

T3

19

T4

13

T5

11

auto[1]

3744

1

T6

2

T7

1

T10

5

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	521	1			T6	3		T12	2		T13	2
values[0]	15	1			T198	13		T295	1		T344	1
values[1]	852	1			T15	14		T58	3		T104	10
values[2]	2946	1			T10	4		T16	4		T17	1
values[3]	576	1			T10	3		T14	5		T62	1
values[4]	658	1			T13	6		T72	25		T151	13
values[5]	508	1			T12	3		T72	14		T186	1
values[6]	597	1			T59	23		T62	1		T236	1
values[7]	476	1			T7	2		T59	14		T239	1
values[8]	596	1			T154	21		T145	15		T270	9
values[9]	905	1			T10	2		T18	19		T177	25
minimum	13521	1			T3	19		T4	13		T5	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	907	1			T15	2		T62	1		T68	2
values[1]	2823	1			T10	4		T16	4		T17	1
values[2]	514	1			T10	3		T14	5		T62	1
values[3]	643	1			T13	6		T151	13		T164	2
values[4]	566	1			T12	3		T72	14		T186	1
values[5]	587	1			T59	23		T62	1		T73	6
values[6]	453	1			T7	2		T59	14		T239	1
values[7]	736	1			T10	2		T18	19		T197	22
values[8]	760	1			T177	25		T187	6		T170	13
values[9]	128	1			T70	9		T140	10		T240	10
minimum	14054	1			T3	19		T4	13		T5	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18399

1

T3

19

T4

13

T5

11

auto[1]

3772

1

T10

1

T13

2

T15

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T15	1		T68	2		T144	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T62	1		T143	12		T267	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1505	1			T16	4		T17	1		T60	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T10	4		T110	1		T143	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T10	2		T14	5		T62	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T72	14		T145	8		T321	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T151	1		T164	2		T53	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	5		T147	1		T277	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T236	1		T191	14		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	2		T72	9		T186	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T59	13		T62	1		T73	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T151	1		T197	10		T34	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T7	1		T59	12		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T239	1		T145	4		T270	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T24	3		T37	1		T244	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T10	1		T18	9		T197	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T177	11		T170	3		T140	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T187	1		T170	10		T197	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T70	6		T240	1		T201	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T140	3		T50	9		T357	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13747	1			T3	19		T4	13		T5	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T15	8		T58	3		T50	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T15	1		T144	12		T217	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T143	11		T241	13		T238	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	922	1			T60	8		T61	6		T111	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T143	9		T90	1		T250	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T10	1		T288	3		T117	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T72	11		T145	9		T321	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T151	12		T53	1		T256	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T13	1		T277	12		T342	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T168	15		T144	11		T141	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T12	1		T72	5		T42	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T59	10		T73	1		T154	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T151	4		T197	9		T42	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T7	1		T59	2		T146	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T145	11		T270	2		T51	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T37	5		T244	19		T266	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T10	1		T18	10		T197	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T177	14		T140	17		T154	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T187	5		T197	9		T267	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T70	3		T240	9		T352	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T140	7		T50	7		T316	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T6	2		T10	3		T12	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T15	4		T50	11		T158	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T6	3		T12	2		T13	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T197	3		T50	9		T357	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T198	1		T344	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T295	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T15	1		T104	1		T68	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T15	8		T58	3		T143	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1529	1			T16	4		T17	1		T60	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T10	4		T62	1		T110	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T10	2		T14	5		T62	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T321	1		T90	2		T250	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T151	1		T164	2		T53	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T13	5		T72	14		T145	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T191	14		T40	1		T168	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T12	2		T72	9		T186	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T59	13		T62	1		T236	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T151	1		T197	10		T34	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T7	1		T59	12		T24	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T239	1		T42	1		T156	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T266	3		T271	14		T288	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T154	11		T145	4		T270	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T177	11		T70	6		T140	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T10	1		T18	9		T187	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13417	1			T3	19		T4	13		T5	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T319	7		T359	1		T343	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T197	9		T50	7		T331	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T198	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T15	1		T104	9		T144	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T15	4		T143	11		T241	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	970	1			T60	8		T61	6		T111	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T143	9		T148	12		T254	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T10	1		T39	1		T113	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T321	14		T90	1		T250	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T151	12		T53	1		T256	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T13	1		T72	11		T145	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T168	15		T144	11		T141	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T12	1		T72	5		T42	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T59	10		T73	1		T154	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T151	4		T197	9		T25	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T7	1		T59	2		T146	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T42	11		T156	9		T269	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T266	1		T271	5		T288	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T154	10		T145	11		T270	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T177	14		T70	3		T140	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T10	1		T18	10		T187	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T6	2		T10	3		T12	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T15	2		T68	2		T144	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T62	1		T143	12		T267	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T16	3		T17	1		T60	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T10	4		T110	1		T143	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T10	2		T14	5		T62	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T72	12		T145	10		T321	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T151	13		T164	1		T53	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T13	4		T147	1		T277	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T236	1		T191	1		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	3		T72	6		T186	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T59	11		T62	1		T73	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T151	5		T197	10		T34	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T7	2		T59	3		T146	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T239	1		T145	12		T270	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T24	2		T37	6		T244	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T10	2		T18	11		T197	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T177	15		T170	1		T140	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T187	6		T170	1		T197	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T70	6		T240	10		T201	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T140	8		T50	8		T357	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13865	1			T3	19		T4	13		T5	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T15	5		T58	2		T50	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T242	14		T182	10		T342	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T143	11		T267	7		T238	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1185	1			T16	1		T142	43		T188	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T143	12		T178	14		T254	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T10	1		T36	8		T148	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T72	13		T145	7		T304	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T164	1		T53	1		T256	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T13	2		T277	6		T360	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T191	13		T141	7		T248	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T72	8		T191	9		T34	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T59	12		T73	1		T154	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T197	9		T34	14		T25	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T59	11		T361	10		T362	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T145	3		T270	6		T156	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T24	1		T244	7		T266	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T18	8		T197	12		T154	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T177	10		T170	2		T140	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T170	9		T197	2		T267	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T70	3		T201	16		T352	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T140	2		T50	8		T201	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T155	14		T291	13		T363	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T15	7		T58	1		T50	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T6	3		T12	2		T13	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T197	10		T50	8		T357	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T198	13		T344	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T295	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T15	2		T104	10		T68	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T15	5		T58	2		T143	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T16	3		T17	1		T60	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T10	4		T62	1		T110	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T10	2		T14	5		T62	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T321	15		T90	3		T250	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T151	13		T164	1		T53	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T13	4		T72	12		T145	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T191	1		T40	1		T168	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T12	3		T72	6		T186	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T59	11		T62	1		T236	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T151	5		T197	10		T34	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T7	2		T59	3		T24	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T239	1		T42	12		T156	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T266	3		T271	6		T288	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T154	11		T145	12		T270	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T177	15		T70	6		T140	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T10	2		T18	11		T187	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13521	1			T3	19		T4	13		T5	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T170	2		T201	16		T359	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T197	2		T50	8		T161	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T155	14		T182	10		T157	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T15	7		T58	1		T143	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1204	1			T16	1		T142	43		T188	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T143	12		T178	14		T148	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T10	1		T36	8		T148	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T304	11		T118	11		T263	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T164	1		T53	1		T256	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	2		T72	13		T145	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T191	13		T141	7		T248	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T72	8		T191	9		T34	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T59	12		T73	1		T154	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T197	9		T34	14		T25	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T59	11		T24	1		T243	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T156	9		T192	9		T269	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T266	1		T271	13		T288	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T154	10		T145	3		T270	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T177	10		T70	3		T140	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T18	8		T170	9		T140	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18399

1

T3

19

T4

13

T5

11

auto[1]

auto[0]

3772

1

T10

1

T13

2

T15

7