Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22171

1

T3

19

T4

13

T5

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

18970

1

T3

19

T4

13

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

3201

1

T7

2

T10

5

T14

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16571

1

T3

19

T4

13

T5

11

auto[1]

5600

1

T10

3

T12

3

T13

6

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18427

1

T3

19

T4

13

T5

11

auto[1]

3744

1

T6

2

T7

1

T10

5

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	207	1			T187	6		T39	2		T25	6
values[0]	5	1			T217	3		T147	1		T235	1
values[1]	648	1			T7	2		T10	2		T68	2
values[2]	779	1			T13	6		T15	2		T59	37
values[3]	535	1			T12	3		T34	15		T42	12
values[4]	597	1			T236	1		T197	12		T237	1
values[5]	2651	1			T10	7		T14	5		T15	12
values[6]	653	1			T110	1		T177	11		T170	3
values[7]	605	1			T16	4		T62	3		T104	10
values[8]	679	1			T72	39		T73	6		T151	5
values[9]	1018	1			T18	19		T58	3		T186	1
minimum	13794	1			T3	19		T4	13		T5	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	750	1			T10	2		T15	2		T59	23
values[1]	678	1			T13	6		T59	14		T177	25
values[2]	524	1			T12	3		T197	12		T238	12
values[3]	2773	1			T15	12		T17	1		T60	9
values[4]	565	1			T10	7		T14	5		T110	1
values[5]	551	1			T62	1		T104	10		T177	11
values[6]	735	1			T16	4		T62	2		T72	25
values[7]	690	1			T72	14		T186	1		T239	1
values[8]	831	1			T18	19		T58	3		T187	6
values[9]	166	1			T50	22		T248	11		T90	3
minimum	13908	1			T3	19		T4	13		T5	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18399

1

T3

19

T4

13

T5

11

auto[1]

3772

1

T10

1

T13

2

T15

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T59	13		T187	1		T143	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T10	1		T15	1		T143	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T13	5		T59	12		T178	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T177	11		T34	15		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T12	2		T197	3		T238	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T242	1		T26	2		T243	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1495	1			T15	8		T17	1		T60	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T236	1		T244	8		T245	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T10	4		T140	3		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T10	2		T14	5		T110	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T104	1		T154	10		T246	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T62	1		T177	1		T170	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T16	4		T62	2		T24	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T72	14		T151	2		T140	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T72	9		T239	1		T170	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T186	1		T191	10		T197	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T18	9		T58	3		T187	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T37	1		T39	1		T247	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T248	6		T268	3		T364	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T50	11		T90	2		T263	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13720	1			T3	19		T4	13		T5	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T7	1		T68	2		T144	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T59	10		T187	2		T143	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T10	1		T15	1		T143	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T13	1		T59	2		T42	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T177	14		T250	1		T218	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T12	1		T197	9		T238	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T120	5		T234	2		T299	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	967	1			T15	4		T60	8		T61	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T244	19		T245	11		T180	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T140	7		T145	9		T252	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T10	1		T70	3		T141	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T104	9		T154	8		T253	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T177	10		T42	2		T53	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T156	9		T254	7		T255	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T72	11		T151	16		T140	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T72	5		T154	11		T145	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T197	9		T256	2		T182	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T18	10		T187	5		T73	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T37	5		T39	1		T257	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T248	5		T269	32		T363	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T50	11		T90	1		T263	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T6	2		T10	3		T12	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T7	1		T144	11		T217	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T187	1		T25	4		T248	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T39	1		T50	11		T280	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T147	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T217	2		T235	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T143	13		T197	13		T164	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T7	1		T10	1		T68	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T13	5		T59	25		T187	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T15	1		T177	11		T191	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T12	2		T42	1		T238	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T34	15		T147	1		T339	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T197	3		T237	1		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T236	1		T244	8		T242	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1451	1			T10	4		T15	8		T17	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T10	2		T14	5		T70	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T140	3		T154	10		T365	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T110	1		T177	1		T170	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T16	4		T62	2		T104	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T62	1		T151	1		T140	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T72	9		T73	5		T170	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T72	14		T151	1		T191	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T18	9		T58	3		T239	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T186	1		T37	1		T90	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13690	1			T3	19		T4	13		T5	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T187	5		T25	2		T248	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T39	1		T50	11		T366	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T217	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T143	9		T197	9		T144	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T7	1		T10	1		T143	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T13	1		T59	12		T187	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T15	1		T177	14		T250	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T12	1		T42	11		T238	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T218	1		T260	10		T299	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T197	9		T146	11		T246	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T244	19		T180	12		T261	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	881	1			T15	4		T60	8		T61	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T10	1		T70	3		T141	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T140	7		T154	8		T252	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T177	10		T42	2		T53	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T104	9		T156	9		T263	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T151	12		T140	17		T144	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T72	5		T73	1		T154	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T72	11		T151	4		T197	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T18	10		T168	15		T240	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T37	5		T90	1		T257	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T6	2		T10	3		T12	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T59	11		T187	3		T143	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T10	2		T15	2		T143	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T13	4		T59	3		T178	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T177	15		T34	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T12	3		T197	10		T238	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T242	1		T26	1		T243	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1279	1			T15	5		T17	1		T60	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T236	1		T244	20		T245	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T10	4		T140	8		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T10	2		T14	5		T110	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T104	10		T154	9		T246	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T62	1		T177	11		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T16	3		T62	2		T24	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T72	12		T151	18		T140	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T72	6		T239	1		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T186	1		T191	1		T197	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T18	11		T58	2		T187	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T37	6		T39	2		T247	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T248	6		T268	1		T364	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T50	12		T90	3		T263	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13809	1			T3	19		T4	13		T5	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T7	2		T68	2		T144	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T59	12		T143	12		T197	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T143	11		T191	13		T154	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	2		T59	11		T178	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T177	10		T34	14		T218	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T197	2		T238	5		T148	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T26	1		T192	9		T264	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1183	1			T15	7		T142	43		T188	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T244	7		T159	10		T195	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T140	2		T145	7		T259	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T10	1		T70	3		T141	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T154	9		T249	1		T265	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T170	2		T53	1		T148	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T16	1		T24	1		T34	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T72	13		T140	17		T267	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T72	8		T170	9		T36	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T191	9		T197	9		T256	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T18	8		T58	1		T73	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T157	11		T249	8		T257	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T248	5		T268	2		T269	30
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T50	10		T263	7		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T192	13		T367	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T215	15		T300	13		T368	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T187	6		T25	5		T248	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T39	2		T50	12		T280	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T147	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T217	3		T235	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T143	10		T197	10		T164	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T7	2		T10	2		T68	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T13	4		T59	14		T187	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T15	2		T177	15		T191	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	3		T42	12		T238	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T34	1		T147	1		T339	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T197	10		T237	1		T146	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T236	1		T244	20		T242	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1193	1			T10	4		T15	5		T17	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T10	2		T14	5		T70	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T140	8		T154	9		T365	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T110	1		T177	11		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T16	3		T62	2		T104	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T62	1		T151	13		T140	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T72	6		T73	5		T170	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T72	12		T151	5		T191	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T18	11		T58	2		T239	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T186	1		T37	6		T90	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13794	1			T3	19		T4	13		T5	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T25	1		T248	5		T269	30
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T50	10		T369	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T143	12		T197	12		T164	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T143	11		T154	10		T270	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T13	2		T59	23		T178	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T177	10		T191	13		T254	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T238	5		T148	8		T288	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T34	14		T218	2		T192	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T197	2		T271	13		T156	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T244	7		T26	1		T159	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1139	1			T15	7		T142	43		T188	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T10	1		T70	3		T141	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T140	2		T154	9		T249	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T170	2		T53	1		T148	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T16	1		T24	1		T34	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T140	17		T267	7		T266	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T72	8		T73	1		T170	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T72	13		T191	9		T197	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T18	8		T58	1		T155	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T157	11		T249	8		T291	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18399

1

T3

19

T4

13

T5

11

auto[1]

auto[0]

3772

1

T10

1

T13

2

T15

7