Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22171

1

T3

19

T4

13

T5

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19103

1

T3

19

T4

13

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

3068

1

T13

6

T15

12

T58

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16692

1

T3

19

T4

13

T5

11

auto[1]

5479

1

T10

2

T12

3

T15

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18427

1

T3

19

T4

13

T5

11

auto[1]

3744

1

T6

2

T7

1

T10

5

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	232	1			T13	6		T191	14		T46	1
values[0]	22	1			T157	12		T251	3		T303	7
values[1]	595	1			T59	14		T104	10		T177	11
values[2]	661	1			T7	2		T15	12		T18	19
values[3]	849	1			T14	5		T58	3		T187	9
values[4]	462	1			T10	3		T186	1		T140	35
values[5]	2836	1			T17	1		T60	9		T61	7
values[6]	651	1			T12	3		T15	2		T62	1
values[7]	663	1			T59	23		T72	25		T73	6
values[8]	712	1			T10	4		T177	25		T236	1
values[9]	694	1			T10	2		T16	4		T72	14
minimum	13794	1			T3	19		T4	13		T5	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	525	1			T59	14		T104	10		T68	2
values[1]	794	1			T7	2		T14	5		T15	12
values[2]	653	1			T187	9		T178	15		T170	3
values[3]	2737	1			T10	3		T17	1		T60	9
values[4]	632	1			T62	2		T110	1		T143	23
values[5]	679	1			T12	3		T15	2		T59	23
values[6]	702	1			T10	4		T72	25		T236	1
values[7]	587	1			T16	4		T177	25		T239	1
values[8]	737	1			T10	2		T13	6		T72	14
values[9]	98	1			T46	1		T155	10		T56	2
minimum	14027	1			T3	19		T4	13		T5	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18399

1

T3

19

T4

13

T5

11

auto[1]

3772

1

T10

1

T13

2

T15

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T59	12		T104	1		T68	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T245	1		T179	1		T247	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T7	1		T14	5		T18	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T15	8		T58	3		T62	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T187	1		T178	15		T145	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T187	1		T170	3		T36	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1534	1			T10	2		T17	1		T60	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T37	1		T53	1		T256	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T62	2		T110	1		T143	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T46	1		T51	1		T182	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T12	2		T15	1		T154	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T59	13		T140	3		T34	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T10	4		T72	14		T236	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T73	5		T240	1		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T16	4		T239	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T177	11		T170	10		T171	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T10	1		T72	9		T143	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T13	5		T145	4		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T46	1		T56	1		T348	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T155	10		T296	1		T300	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13723	1			T3	19		T4	13		T5	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T151	1		T141	8		T247	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T59	2		T104	9		T177	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T245	11		T288	2		T180	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	1		T18	10		T42	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T15	4		T197	9		T39	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T187	2		T145	9		T53	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T187	5		T298	5		T250	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	916	1			T10	1		T60	8		T61	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T37	5		T256	2		T246	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T143	11		T70	3		T197	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T51	11		T182	24		T268	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	1		T15	1		T154	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T59	10		T140	7		T50	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T72	11		T144	12		T244	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T73	1		T240	9		T146	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T151	4		T42	11		T50	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T177	14		T144	9		T267	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T10	1		T72	5		T143	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T13	1		T145	11		T50	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T56	1		T348	12		T299	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T296	16		T300	14		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	2		T10	3		T12	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T151	12		T141	8		T258	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T191	14		T46	1		T365	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T13	5		T50	9		T287	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T251	1		T303	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T157	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T59	12		T104	1		T177	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T151	1		T141	8		T245	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	1		T18	9		T68	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T15	8		T62	1		T197	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T14	5		T187	1		T178	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T58	3		T187	1		T170	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T10	2		T186	1		T140	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T37	1		T164	2		T53	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1590	1			T17	1		T60	1		T61	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T46	1		T51	1		T256	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	2		T15	1		T62	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T34	15		T267	8		T50	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T72	14		T144	1		T237	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T59	13		T73	5		T140	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T10	4		T236	1		T239	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T177	11		T170	10		T171	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T10	1		T16	4		T72	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T145	4		T141	1		T259	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13690	1			T3	19		T4	13		T5	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T56	1		T348	12		T299	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T13	1		T50	7		T287	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T251	2		T303	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T59	2		T104	9		T177	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T151	12		T141	8		T245	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	1		T18	10		T197	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T15	4		T197	9		T168	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T187	2		T145	9		T90	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T187	5		T39	1		T298	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T10	1		T140	17		T217	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T37	5		T246	1		T288	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	980	1			T60	8		T61	6		T111	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T51	11		T256	2		T182	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	1		T15	1		T154	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T50	14		T271	5		T304	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T72	11		T144	12		T244	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T59	10		T73	1		T140	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T151	4		T42	11		T25	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T177	14		T144	9		T267	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T10	1		T72	5		T143	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T145	11		T342	1		T284	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T6	2		T10	3		T12	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T59	3		T104	10		T68	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T245	12		T179	1		T247	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T7	2		T14	5		T18	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T15	5		T58	2		T62	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T187	3		T178	1		T145	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T187	6		T170	1		T36	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1233	1			T10	2		T17	1		T60	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T37	6		T53	1		T256	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T62	2		T110	1		T143	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T46	1		T51	12		T182	25
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	3		T15	2		T154	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T59	11		T140	8		T34	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T10	4		T72	12		T236	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T73	5		T240	10		T146	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T16	3		T239	1		T151	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T177	15		T170	1		T171	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T10	2		T72	6		T143	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T13	4		T145	12		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T46	1		T56	2		T348	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T155	1		T296	17		T300	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13842	1			T3	19		T4	13		T5	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T151	13		T141	9		T247	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T59	11		T197	9		T154	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T288	4		T283	14		T117	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T18	8		T34	3		T154	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T15	7		T58	1		T197	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T178	14		T145	7		T53	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T170	2		T36	8		T164	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1217	1			T10	1		T142	43		T188	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T256	2		T291	13		T159	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T143	11		T70	3		T191	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T182	10		T268	9		T249	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T154	10		T257	3		T305	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T59	12		T140	2		T34	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T72	13		T244	7		T25	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T73	1		T148	8		T254	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T16	1		T50	10		T277	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T177	10		T170	9		T267	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T72	8		T143	12		T191	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T13	2		T145	3		T50	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T292	9		T306	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T155	9		T300	13		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T289	9		T263	7		T302	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T141	7		T157	11		T258	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T191	1		T46	1		T365	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T13	4		T50	8		T287	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T251	3		T303	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T157	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T59	3		T104	10		T177	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T151	13		T141	9		T245	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T7	2		T18	11		T68	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T15	5		T62	1		T197	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T14	5		T187	3		T178	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T58	2		T187	6		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T10	2		T186	1		T140	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T37	6		T164	1		T53	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1309	1			T17	1		T60	9		T61	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T46	1		T51	12		T256	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T12	3		T15	2		T62	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T34	1		T267	1		T50	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T72	12		T144	13		T237	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T59	11		T73	5		T140	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T10	4		T236	1		T239	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T177	15		T170	1		T171	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T10	2		T16	3		T72	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T145	12		T141	1		T259	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13794	1			T3	19		T4	13		T5	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T191	13		T194	6		T292	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T13	2		T50	8		T213	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T157	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T59	11		T154	9		T289	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T141	7		T288	4		T283	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T18	8		T197	9		T34	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T15	7		T197	12		T243	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T178	14		T145	7		T156	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T58	1		T170	2		T36	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T10	1		T140	17		T270	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T164	1		T288	2		T159	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1261	1			T142	43		T188	16		T143	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T256	2		T182	10		T268	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T154	10		T218	2		T183	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T34	14		T267	7		T50	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T72	13		T244	7		T254	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T59	12		T73	1		T140	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T25	1		T50	10		T277	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T177	10		T170	9		T267	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T16	1		T72	8		T143	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T145	3		T259	14		T155	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18399

1

T3

19

T4

13

T5

11

auto[1]

auto[0]

3772

1

T10

1

T13

2

T15

7