Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22171

1

T3

19

T4

13

T5

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19019

1

T3

19

T4

13

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

3152

1

T10

6

T12

3

T13

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16692

1

T3

19

T4

13

T5

11

auto[1]

5479

1

T7

2

T10

6

T12

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18427

1

T3

19

T4

13

T5

11

auto[1]

3744

1

T6

2

T7

1

T10

5

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	178	1			T7	2		T14	5		T15	12
values[0]	65	1			T350	3		T260	23		T333	8
values[1]	705	1			T59	23		T110	1		T177	11
values[2]	554	1			T104	10		T187	6		T140	10
values[3]	480	1			T10	4		T62	1		T151	5
values[4]	590	1			T177	25		T239	1		T170	3
values[5]	814	1			T236	1		T187	3		T143	23
values[6]	546	1			T72	25		T73	6		T34	4
values[7]	548	1			T10	5		T13	6		T18	19
values[8]	2894	1			T12	3		T15	2		T16	4
values[9]	1003	1			T62	1		T42	12		T154	14
minimum	13794	1			T3	19		T4	13		T5	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	550	1			T110	1		T187	6		T140	10
values[1]	575	1			T104	10		T151	5		T34	15
values[2]	467	1			T10	4		T62	1		T170	10
values[3]	605	1			T177	25		T239	1		T170	3
values[4]	836	1			T236	1		T187	3		T143	23
values[5]	473	1			T10	3		T58	3		T72	25
values[6]	2779	1			T10	2		T13	6		T15	2
values[7]	748	1			T12	3		T59	14		T62	1
values[8]	879	1			T7	2		T14	5		T62	1
values[9]	134	1			T15	12		T256	5		T274	1
minimum	14125	1			T3	19		T4	13		T5	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18399

1

T3

19

T4

13

T5

11

auto[1]

3772

1

T10

1

T13

2

T15

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T110	1		T187	1		T40	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T140	3		T146	1		T46	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T151	1		T51	1		T155	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T104	1		T34	15		T168	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T62	1		T170	10		T154	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T10	4		T197	16		T171	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T144	2		T50	14		T256	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T177	11		T239	1		T170	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T143	12		T42	1		T244	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T236	1		T187	1		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T10	2		T186	1		T73	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T58	3		T72	14		T262	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1523	1			T16	4		T17	1		T60	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T10	1		T13	5		T15	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T62	1		T72	9		T143	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	2		T59	12		T68	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T7	1		T154	3		T141	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T14	5		T62	1		T191	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T15	8		T256	3		T274	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T292	10		T353	1		T30	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13823	1			T3	19		T4	13		T5	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T59	13		T147	1		T248	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T187	5		T363	14		T198	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T140	7		T146	11		T275	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T151	4		T51	11		T156	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T104	9		T168	15		T298	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T154	10		T246	1		T245	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T197	18		T267	6		T284	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T144	20		T50	14		T266	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T177	14		T197	9		T39	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T143	11		T42	2		T244	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T187	2		T151	12		T154	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T10	1		T73	1		T145	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T72	11		T262	10		T304	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	941	1			T60	8		T61	6		T111	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T10	1		T13	1		T15	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T72	5		T143	9		T70	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T12	1		T59	2		T42	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T7	1		T154	11		T141	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T140	17		T217	1		T270	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T15	4		T256	2		T113	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T353	6		T30	2		T370	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T6	2		T10	3		T12	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T59	10		T248	5		T354	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T7	1		T15	8		T141	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T14	5		T191	14		T140	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T350	3		T260	13		T333	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T371	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T110	1		T177	1		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T59	13		T146	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T187	1		T51	1		T156	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T104	1		T140	3		T34	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T62	1		T151	1		T170	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T10	4		T197	16		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T144	1		T50	14		T256	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T177	11		T239	1		T170	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T143	12		T144	1		T53	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T236	1		T187	1		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T73	5		T34	4		T42	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T72	14		T259	15		T242	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T10	2		T72	9		T186	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T10	1		T13	5		T18	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1584	1			T16	4		T17	1		T60	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	2		T15	1		T59	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T154	3		T256	3		T242	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T62	1		T42	1		T164	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13690	1			T3	19		T4	13		T5	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T7	1		T15	4		T141	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T140	17		T318	8		T359	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T260	10		T349	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T177	10		T50	7		T262	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T59	10		T146	11		T248	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T187	5		T51	11		T156	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T104	9		T140	7		T168	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T151	4		T154	10		T246	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T197	18		T298	5		T250	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T144	9		T50	14		T288	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T177	14		T197	9		T39	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T143	11		T144	11		T266	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T187	2		T151	12		T154	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T73	1		T42	2		T244	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T72	11		T262	10		T304	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T10	1		T72	5		T145	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T10	1		T13	1		T18	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	992	1			T60	8		T61	6		T111	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T12	1		T15	1		T59	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T154	11		T256	2		T156	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T42	11		T217	1		T270	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T6	2		T10	3		T12	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T110	1		T187	6		T40	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T140	8		T146	12		T46	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T151	5		T51	12		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T104	10		T34	1		T168	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T62	1		T170	1		T154	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T10	4		T197	20		T171	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T144	22		T50	15		T256	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T177	15		T239	1		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T143	12		T42	3		T244	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T236	1		T187	3		T151	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T10	2		T186	1		T73	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T58	2		T72	12		T262	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1258	1			T16	3		T17	1		T60	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T10	2		T13	4		T15	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T62	1		T72	6		T143	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	3		T59	3		T68	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T7	2		T154	12		T141	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T14	5		T62	1		T191	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T15	5		T256	3		T274	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T292	1		T353	7		T30	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13921	1			T3	19		T4	13		T5	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T59	11		T147	1		T248	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T161	13		T363	15		T329	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T140	2		T340	13		T159	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T155	14		T156	23		T118	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T34	14		T250	11		T268	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T170	9		T154	10		T288	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T197	14		T267	7		T157	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T50	13		T266	1		T148	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T177	10		T170	2		T197	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T143	11		T244	7		T271	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T36	8		T154	9		T259	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T10	1		T73	1		T24	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T58	1		T72	13		T262	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1206	1			T16	1		T142	43		T188	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T13	2		T18	8		T267	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T72	8		T143	12		T70	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T59	11		T164	1		T148	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T154	2		T141	7		T156	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T191	13		T140	17		T270	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T15	7		T256	2		T213	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T292	9		T30	2		T370	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T50	8		T262	2		T283	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T59	12		T248	5		T305	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T7	2		T15	5		T141	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T14	5		T191	1		T140	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T350	3		T260	11		T333	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T371	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T110	1		T177	11		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T59	11		T146	12		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T187	6		T51	12		T156	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T104	10		T140	8		T34	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T62	1		T151	5		T170	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T10	4		T197	20		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T144	10		T50	15		T256	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T177	15		T239	1		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T143	12		T144	12		T53	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T236	1		T187	3		T151	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T73	5		T34	1		T42	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T72	12		T259	1		T242	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T10	2		T72	6		T186	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T10	2		T13	4		T18	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1321	1			T16	3		T17	1		T60	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	3		T15	2		T59	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T154	12		T256	3		T242	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T62	1		T42	12		T164	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13794	1			T3	19		T4	13		T5	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T15	7		T141	7		T213	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T191	13		T140	17		T359	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T260	12		T333	7		T349	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T50	8		T262	2		T283	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T59	12		T248	5		T340	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T156	23		T118	11		T331	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T140	2		T34	14		T268	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T170	9		T154	10		T155	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T197	14		T250	11		T157	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T50	13		T288	4		T342	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T177	10		T170	2		T197	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T143	11		T266	1		T148	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T36	8		T154	9		T50	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T73	1		T34	3		T244	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T72	13		T259	14		T242	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T10	1		T72	8		T178	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	2		T18	8		T58	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1255	1			T16	1		T142	43		T188	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T59	11		T192	9		T54	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T154	2		T256	2		T156	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T164	1		T270	6		T25	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18399

1

T3

19

T4

13

T5

11

auto[1]

auto[0]

3772

1

T10

1

T13

2

T15

7